SLUSEK7 September   2024 BQ25773

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics BQ2577X
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequence
      2. 7.3.2  MODE Pin Detection
      3. 7.3.3  REGN Regulator (REGN LDO)
      4. 7.3.4  Independent Comparator Function
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Charging Safety Timer
      6. 7.3.6  Temperature Regulation (TREG)
      7. 7.3.7  Vmin Active Protection (VAP) When Battery Only Mode
      8. 7.3.8  Two Level Battery Discharge Current Limit
      9. 7.3.9  Fast Role Swap Feature
      10. 7.3.10 CHRG_OK Indicator
      11. 7.3.11 Input and Charge Current Sensing
      12. 7.3.12 Input Current and Voltage Limit Setup
      13. 7.3.13 Battery Cell Configuration
      14. 7.3.14 Device HIZ State
      15. 7.3.15 USB On-The-Go (OTG)
      16. 7.3.16 Quasi Dual Phase Converter Operation
      17. 7.3.17 Continuous Conduction Mode (CCM)
      18. 7.3.18 Pulse Frequency Modulation (PFM)
      19. 7.3.19 Switching Frequency and Dithering Feature
      20. 7.3.20 Current and Power Monitor
        1. 7.3.20.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 7.3.20.2 High-Accuracy Power Sense Amplifier (PSYS)
      21. 7.3.21 Input Source Dynamic Power Management
      22. 7.3.22 Integrated 16-Bit ADC for Monitoring
      23. 7.3.23 Input Current Optimizer (ICO)
      24. 7.3.24 Two-Level Adapter Current Limit (Peak Power Mode)
      25. 7.3.25 Processor Hot Indication
        1. 7.3.25.1 PROCHOT During Low Power Mode
        2. 7.3.25.2 PROCHOT Status
      26. 7.3.26 Device Protection
        1. 7.3.26.1  Watchdog Timer (WD)
        2. 7.3.26.2  Input Overvoltage Protection (ACOV)
        3. 7.3.26.3  Input Overcurrent Protection (ACOC)
        4. 7.3.26.4  System Overvoltage Protection (SYSOVP)
        5. 7.3.26.5  Battery Overvoltage Protection (BATOVP)
        6. 7.3.26.6  Battery Charge Overcurrent Protection (BATCOC)
        7. 7.3.26.7  Battery Discharge Overcurrent Protection (BATDOC)
        8. 7.3.26.8  BATFET Charge Current Clamp Protection under LDO Regulation Mode
        9. 7.3.26.9  Sleep Comparator Protection Between VBUS and ACP_A (SC_VBUSACP)
        10. 7.3.26.10 High Duty Buck Exit Comparator Protection (HDBCP)
        11. 7.3.26.11 REGN Power Good Protection (REGN_PG)
        12. 7.3.26.12 System Under Voltage Lockout (VSYS_UVP) and Hiccup Mode
        13. 7.3.26.13 OTG Mode Over Voltage Protection (OTG_OVP)
        14. 7.3.26.14 OTG Mode Under Voltage Protection (OTG_UVP)
        15. 7.3.26.15 Thermal Shutdown (TSHUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forward Mode
        1. 7.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 7.4.1.2 Battery Charging
      2. 7.4.2 USB On-The-Go Mode
      3. 7.4.3 Pass Through Mode (PTM)-Patented Technology
      4. 7.4.4 Learn Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
        1. 7.5.1.1 Timing Diagrams
        2. 7.5.1.2 Data Validity
        3. 7.5.1.3 START and STOP Conditions
        4. 7.5.1.4 Byte Format
        5. 7.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)
        6. 7.5.1.6 Target Address and Data Direction Bit
        7. 7.5.1.7 Single Read and Write
        8. 7.5.1.8 Multi-Read and Multi-Write
        9. 7.5.1.9 Write 2-Byte I2C Commands
    6. 7.6 BQ25773 Registers
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 8.2.2.2 ACP-ACN Input Filter
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Power MOSFETs Selection
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layout Example Reference Top View
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REE|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current (plus system current there is any system load) when duty cycle is 0.5 in buck mode. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current occurs where the duty cycle is closest to 50% and can be estimated by Equation 5:

Equation 5. BQ25773

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed in front of RAC current sensing and as close as possible to the power stage half bridge MOSFETs. Capacitance after RAC before power stage half bridge should be limited to10μF+10nF+1nF referring to Figure 8-3 diagram. Voltage rating of the capacitor must be higher than normal input voltage level, 35 V rating or higher capacitor is preferred for 28 V input voltage. Minimum 10 pieces of 10-µF 0603 size capacitors are suggested for 28V/140 W adapter design. 50-V rating or higher capacitor is preferred for 36-V input voltage. Minimum 10*10μF 0805 capacitors are needed when power reaches 36 V/180 W. Under different input voltage the minimum input capacitance requirement is summarized in Table 8-7, Table 8-3 and Table 8-4. For quasi dual phase it is recommended to spread the MLCC caps before RAC_A and RAC_B. 1*10nF+1nF 0402 package MLCC capacitors (EMI filter purpose) are recommended to be placed as close as possible to both phase A and phase B half bridge MOSFETs.

Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's data sheet about the derating performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required capacitance value at the operating point. Tantalum capacitors (POSCAP) can avoid dc-bias effect and temperature variation effect which is recommended especially for 28-V and 36-V higher power application.

Table 8-2 Input Capacitance Requirement for 20-V/100-W System
20-V/100-W SYSTEM MINIMUM TYPICAL MAXIMUM
Effective input capacitance

4 μF (MLCC) OTG is not needed

8 μF (MLCC) OTG is needed

4 μF (MLCC) + 15 μF (POSCAP) 4 μF (MLCC) + 2*33 μF (POSCAP)
Practical input capacitors configuration

4*10 μF OTG is not needed

(0603 35 V MLCC derating to around 10% under 20-V bias voltage)

4*10 μF (0603 35 V MLCC derating to around 10% under 20-V bias voltage)

1*15 μF (2917 35 V POSCAP)

4*10 μF (0603 35 V MLCC derating to around 10% under 20-V bias voltage)

2*33 μF (2917 35 V POSCAP)

Table 8-3 Input Capacitance Requirement for 28-V/140-W System
28-V/140-W SYSTEM MINIMUM TYPICAL MAXIMUM
Effective input capacitance

6 μF (MLCC) OTG is not needed

8 μF (MLCC) OTG is needed

6 μF (MLCC) + 15 μF (POSCAP) 6 μF (MLCC) + 2*33 μF (POSCAP)
Practical input capacitors configuration

10*10 μF OTG is not needed

(0603 35 V MLCC derating to around 6% under 28-V bias voltage)

10*10 μF (0603 35 V MLCC derating to around 6% under 28-V bias voltage )

1*15 μF (2917 35 V POSCAP)

10*10 μF (0603 35 V MLCC derating to around 6% under 28-V bias voltage )

2*33 μF (2917 35 V POSCAP)
Table 8-4 Input Capacitance Requirement for 36-V/180-W System
36-V/180-W SYSTEM MINIMUM TYPICAL MAXIMUM
Effective input capacitance 8 μF (MLCC) 8 μF (MLCC) + 15 μF (POSCAP) 8 μF (MLCC) + 2*33 μF (POSCAP)
Practical input capacitors configuration

10*10 μF (0805 50 V MLCC derating to around 8% under 36-V bias voltage)

10*10 μF (0805 50 V MLCC derating to around 8% under 36-V bias voltage)

1*15 μF (2917 50 V POSCAP)

10*10 μF (0805 50 V MLCC derating to around 8% under 36-V bias voltage)

2*33 μF (2917 50 V POSCAP)