SLUSEK7 September 2024 BQ25773
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VINPUT_OP | Input voltage operating range | 3.5 | 40.00 | V | ||
MAX SYSTEM VOLTAGE REGULATION | ||||||
VSYSMAX_RNG | System Voltage Regulation, measured on VSYS (charge disabled) | 5.16 | 23.16 | V | ||
VSYSMAX_ACC | System voltage regulation accuracy (charge disabled) | CHARGE_VOLTAGE() = 0x1482 (21.000 V) | VSRN + 200 mV | V | ||
–0.6% | 0.6% | |||||
CHARGE_VOLTAGE() = 0x1068H (16.800 V) | VSRN + 200 mV | V | ||||
–0.6% | 0.6% | |||||
CHARGE_VOLTAGE() = 0x0C4EH (12.600 V) | VSRN + 200 mV | V | ||||
–0.6% | 0.6% | |||||
CHARGE_VOLTAGE() = 0x0834H (8.400 V) | VSRN + 200 mV | V | ||||
–1% | 1% | |||||
MINIMUM SYSTEM VOLTAGE REGULATION | ||||||
VSYSMIN_RNG | System Voltage Regulation, measured on VSYS | 5.00 | 23.00 | V | ||
VSYSMIN_REG_ACC | Minimum System Voltage Regulation Accuracy (VBAT below REG0x3E() setting) | VSYS_MIN() = 0x0C08H | 15.40 | V | ||
–0.9% | 0.9% | |||||
VSYS_MIN() = 0x099CH | 12.30 | V | ||||
–0.9% | 0.9% | |||||
VSYS_MIN() = 0x0730H | 9.20 | V | ||||
–1.3% | 1.1% | |||||
VSYS_MIN() = 0x0528H | 6.60 | V | ||||
–1.5% | 1.50% | |||||
CHARGE VOLTAGE REGULATION | ||||||
VBAT_RNG | Battery voltage regulation | 5.00 | 23.00 | V | ||
VBAT_REG_ACC | Battery voltage regulation accuracy (charge enable) (0°C to 85°C) | CHARGE_VOLTAGE() = 0x1482H | 21.0 | V | ||
–0.5% | 0.6% | |||||
CHARGE_VOLTAGE()= 0x1068H | 16.8 | V | ||||
–0.5% | 0.6% | |||||
CHARGE_VOLTAGE() = 0x0C4EH | 12.6 | V | ||||
–0.5% | 0.6% | |||||
CHARGE_VOLTAGE() = 0x0834H | 8.4 | V | ||||
–0.5% | 0.6% | |||||
CHARGE CURRENT REGULATION IN FAST CHARGE | ||||||
VIREG_CHG_RNG | Charge current regulation differential voltage range with 5-mΩ sensing resistor | VIREG_CHG = VSRP – VSRN | 128 | 16320 | mA | |
ICHRG_REG_ACC | Charge current regulation accuracy 5-mΩ sensing resistor, VBAT above VSYS_MIN() setting (0°C to 85°C) | CHARGE_CURRENT() = 0x600H, VBAT=7.4V/11.1V/14.8V/18.5V | 12288 | mA | ||
–1.5% | 1.5% | |||||
CHARGE_CURRENT() = 0x400H, VBAT=7.4V/11.1V/14.8V/18.5V | 8192 | mA | ||||
–2.0% | 2.0% | |||||
CHARGE_CURRENT() = 0x200H, VBAT=7.4V/11.1V/14.8V/18.5V | 4096 | mA | ||||
–3.0% | 3.0% | |||||
CHARGE_CURRENT() = 0x100H, VBAT=7.4V/11.1V/14.8V/18.5V | 2048 | mA | ||||
–5.0% | 5.0% | |||||
CHARGE_CURRENT() = 0x080H VBAT=7.4V/11.1V/14.8V/18.5V | 1024 | mA | ||||
–8.0% | 8.0% | |||||
CHARGE CURRENT REGULATION IN PRE-CHARGE(LDO MODE) | ||||||
VPRECHG_RANGE | Pre-charge Current Range 5-mΩ SRP/SRN series resistor, VBAT below REG0x3E() setting (0°C to 85°C) | VIREG_PRECHG = VSRP - VSRN, IPRECHG() = 0x10H~0xFCH | 128 | 2016 | mA | |
IPRECHRG_REG_ACC | Pre-charge current regulation accuracy with 5-mΩ SRP/SRN series resistor, VBAT below VSYS_MIN() setting (0°C to 85°C) RSNS_RSR=0b | IPRECHG() = 0x80H,CHARGE_CURRENT() = 0x100H | 1024 | mA | ||
–10.0% | 10.0% | |||||
IPRECHG() = 0x40H,CHARGE_CURRENT() = 0x100H | 512 | mA | ||||
–15.0% | 15.0% | |||||
IPRECHG() = 0x20H,CHARGE_CURRENT() = 0x100H | 256 | mA | ||||
–20.0% | 20.0% | |||||
IPRECHG() = 0x10H,CHARGE_CURRENT() = 0x100H | 128 | mA | ||||
–30.0% | 30.0% | |||||
TERMINATION CURRENT AND RECHARGE(AUTONOMOUS CHARGING) | ||||||
VTERM_RANGE | Termination Current Range 5-mΩ SRP/SRN series resistor, VBAT below REG0x3E() setting (0°C to 85°C) | VIREG_TERM = VSRP - VSRN, ITERM() = 0x10H~0xFCH | 128 | 2016 | mA | |
VRECHG | Battery automatic recharge threshold(0°C to 85°C) | VSRN falling threshold as negative offset based on CHARGE_VOLTAGE()=12.6V, VRECHG()=1111b | 800.0 | mV | ||
VSRN falling threshold as negative offset based on CHARGE_VOLTAGE()=12.6V,VRECHG()=0111b | 400.0 | mV | ||||
VSRN falling threshold as negative offset based on CHARGE_VOLTAGE()=12.6V,VRECHG()=0011b | 200.0 | mV | ||||
VSRN falling threshold as negative offset based on CHARGE_VOLTAGE()=12.6V,VRECHG()=0001b | 100.0 | mV | ||||
INPUT CURRENT REGULATION | ||||||
VIREG_DPM_RNG | Input current regulation range with 10-mΩ ACP/ACN series resistor | VIREG_DPM = VACP_A – VACN_A +VACP_B - VACN_B | 400 | 8200 | mA | |
IIIN_DPM_REG_ACC | Input current regulation accuracy with 10-mΩ ACP/ACN series resistor | IIN_HOST() = 0x0C4H | 4750 | 4900 | 5000 | mA |
IIN_HOST() = 0x074H | 2800 | 2900 | 3000 | mA | ||
IIN_HOST() = 0x024H | 800 | 900 | 1000 | mA | ||
IIN_HOST() = 0x010H | 300 | 400 | 510 | mA | ||
VIREG_DPM_RNG_ILIM | Voltage range for input current regulation (ILIM_HIZ Pin) | 1.15 | 4.0 | V | ||
IIIN_DPM_REG_ACC_ILIM | Input Current Regulation Accuracy on ILIM_HIZ pin VILIM_HIZ = 1 V + 40 × IIIN_DPM × RAC, with 10-mΩ ACP/ACN series resistor | VILIM_HIZ = 3.0 V | 4800 | 5000 | 5200 | mA |
VILIM_HIZ = 2.2 V | 2800 | 3000 | 3200 | mA | ||
VILIM_HIZ = 1.4 V | 800 | 1000 | 1200 | mA | ||
VILIM_HIZ = 1.2 V | 300 | 500 | 700 | mA | ||
ILEAK_ILIM | ILIM_HIZ pin leakage current | –1 | 1 | µA | ||
INPUT VOLTAGE REGULATION | ||||||
VVINPM_REG_ACC | Input voltage regulation accuracy | VINDPM()=0x384H | 18000 | mV | ||
–1% | 1% | |||||
VINDPM()=0x0E0H | 4480 | mV | ||||
–3% | 3% | |||||
OTG CURRENT REGULATION | ||||||
VIOTG_REG_RNG | OTG output current regulation range with 10-mΩ ACP/ACN series resistor | VIOTG_REG = VACP_A – VACN_A +VACP_B - VACN_B | 100 | 3000 | mA | |
IOTG_ACC | OTG output current regulation accuracy with 25-mA LSB and 10-mΩ ACP/ACN series resistor | OTG_Current() = 0x078H | 2850 | 3000 | 3150 | mA |
OTG_Current() = 0x03CH | 1350 | 1500 | 1650 | mA | ||
OTG_Current() = 0x014H | 350 | 500 | 650 | mA | ||
OTG VOLTAGE REGULATION | ||||||
VOTG_REG_RNG | OTG voltage regulation range | Voltage on VBUS | 3 | 5 | V | |
VOTG_REG_ACC | OTG voltage regulation accuracy | OTG_Voltage()=0x0FAH | 5.00 | V | ||
VOTG_REG_ACC | OTG voltage regulation accuracy | –3% | 3% | |||
REGN REGULATOR | ||||||
VREGN_REG | REGN regulator voltage | VBUS = 10 V, REGN_EXT=0b | 4.80 | 5.00 | 5.10 | V |
VREGN_REG_EXT | REGN regulator voltage with external over drive | VBUS = 10 V, REGN_EXT=1b | 4.35 | 4.50 | 4.65 | V |
IREGN_LIM_CHARGING | REGN current limit when converter is enabled | VBUS = 10 V, force VREGN =4 V | 150.00 | 191.00 | mA | |
IREGN_LIM_LWPWR | REGN current limit when in battery only low power mode | VBUS = 0 V, VVBAT = 18 V, force VREGN =4 V, EN_LWPWR=1b, EN_REGN_LWPWR=1b, | 3.00 | 12.00 | mA | |
VREGN_OK_FALL | REGN regulator voltage valid falling threshold | 2.8 | 3.20 | V | ||
VREGN_OK_RISE | REGN regulator voltage valid rising threshold | 3.10 | 3.40 | 3.60 | V | |
VREGN_OV_RISE | REGN regulator voltage over voltage rising threshold | 5.30 | 5.50 | 5.60 | V | |
VREGN_OV_FALL | REGN regulator voltage over voltage falling threshold | 5.10 | 5.30 | 5.50 | V | |
QUIESCENT CURRENT | ||||||
ISD_BAT | System powered by battery. ISRN + ISRP + ISW2 + IBTST2 + ISW1_A&B + IBTST1_A&B + IACP_A&B + IACN_A&B + IVBUS + IVSYS | VBAT = 18 V, in low power mode(EN_LWPWR = 1b), Comparator off(EN_LWPWR_CMP=0b, CMP_EN=1b), BATDRV is Off (BATFET_ENZ=1b), REGN is off(EN_REGN_LWPWR=0b), PSYS is off(PSYS_CONFIG=11b), Continuous ADC is off(ADC_RATE=1b) | 12.0 | 20.0 | µA | |
IQ_BAT1 | System powered by battery. ISRN + ISRP + ISW2 + IBTST2 + ISW1_A&B + IBTST1_A&B + IACP_A&B + IACN_A&B + IVBUS + IVSYS | VBAT = 18 V, in low power mode(EN_LWPWR = 1b), Comparator off(EN_LWPWR_CMP=0b), BATDRV is On (BATFET_ENZ=0b, CMP_EN=1b), REGN is off(EN_REGN_LWPWR=0b), PSYS is off(PSYS_CONFIG=11b), IBAT is off(EN_IBAT=0b), Continuous ADC is off(ADC_RATE=1b) | 20 | 30 | µA | |
IQ_BAT2 | System powered by battery. ISRN + ISRP + ISW2 + IBTST2 + ISW1_A&B + IBTST1_A&B + IACP_A&B + IACN_A&B + IVBUS + IVSYS | VBAT = 18 V, in low power mode(EN_LWPWR = 1b), Comparator on(EN_LWPWR_CMP=1b, CMP_EN=1b), BATDRV is On (BATFET_ENZ=0b), REGN is off (EN_REGN_LWPWR=0b), PSYS is off(PSYS_CONFIG=11b), IBAT is off(EN_IBAT=0b), Continuous ADC is off(ADC_RATE=1b) | 30 | 45 | µA | |
IQ_BAT3 | System powered by battery. ISRN + ISRP + ISW2 + IBTST2 + ISW1_A&B + IBTST1_A&B + IACP_A&B + IACN_A&B + IVBUS + IVSYS | VBAT = 18 V, in low power mode(EN_LWPWR = 1b, CMP_EN=1b), Comparator on(EN_LWPWR_CMP=1b),BATDRV is On (BATFET_ENZ=0b), REGN is on scaled down to 5mA (EN_REGN_LWPWR=1b), PSYS is off(PSYS_CONFIG=11b), IBAT is off(EN_IBAT=0b), Continuous ADC is off(ADC_RATE=1b) | 110 | 150 | µA | |
IQ_BAT4 | System powered by battery. ISRN + ISRP + ISW2 + IBTST2 + ISW1_A&B + IBTST1_A&B + IACP_A&B + IACN_A&B + IVBUS + IVSYS | VBAT = 18 V, in performance mode(EN_LWPWR = 0b, CMP_EN=1b), Comparator on(EN_LWPWR_CMP=1b),BATDRV is On (BATFET_ENZ=0b), REGN is on in full power,PSYS is on(PSYS_CONFIG=00b), IBAT is on(EN_IBAT=1b), Continuous ADC is off(ADC_RATE=1b) | 800 | 1000 | µA | |
IQ_BAT5 | System powered by battery. ISRN + ISRP + ISW2 + IBTST2 + ISW1_A&B + IBTST1_A&B + IACP_A&B + IACN_A&B + IVBUS + IVSYS | VBAT = 18 V, in performance mode(EN_LWPWR = 0b), Comparator on(EN_LWPWR_CMP=1b, CMP_EN=1b),BATDRV is On (BATFET_ENZ=0b), REGN is on in full power,PSYS is On(PSYS_CONFIG=00b), IBAT is on(EN_IBAT=1b),Continuous ADC is on(ADC_RATE=0b, ADC_EN=1b, enable at least 1 channel EN_ADC_VBAT=1b) | 950 | 1100 | µA | |
IQ_HIZ | Converter under HIZ mode and system powered by battery. ISRN + ISRP + ISW2 + IBTST2 + ISW1_A&B + IBTST1_A&B + IACP_A&B + IACN_A&B + IVBUS + IVSYS | VIN = 28 V, VBAT = 12.6 V, 3s, EN_HIZ=1b; in HIZ mode | 1000 | 1150 | µA | |
IQ_VAC | Input current in buck mode, no load, IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST + ISW2 + IBTST2 | VIN = 28 V, VBAT = 12.6 V, 3s, EN_LEARN=1b, no switching | 1000 | 1150 | mA | |
VIN = 28 V, VBAT = 12.6 V, 3s, EN_OOA = 0b; switching at zero load | 2.50 | mA | ||||
CURRENT SENSE AMPLIFIER | ||||||
VIADPT_CLAMP | IADPT output clamp voltage | 3.1 | 3.2 | 3.3 | V | |
IIADPT | IADPT output current | 1 | 2.5 | mA | ||
AIADPT | Input current sensing gain | V(IADPT) / (VACP_A-VACN_A+VACP_B-VACN_B), IADPT_GAIN = 0 | 20 | V/V | ||
V(IADPT) / (VACP_A-VACN_A+VACP_B-VACN_B), IADPT_GAIN = 1 | 40 | V/V | ||||
VIADPT_ACC | Input current monitor accuracy | VACP_A-VACN_A+VACP_B-VACN_B = 61.44 mV, IADPT_GAIN = 0 | –2.5% | 1.5% | ||
VACP_A-VACN_A+VACP_B-VACN_B = 40.96 mV, IADPT_GAIN = 0 | –3.5% | 2% | ||||
IADPT_GAIN = 0VACP_A-VACN_A+VACP_B-VACN_B = 20.48 mV, IADPT_GAIN = 0 | –6% | 3% | ||||
VACP_A-VACN_A+VACP_B-VACN_B =10.24 mV, IADPT_GAIN = 0 | –15% | 6% | ||||
VACP_A-VACN_A+VACP_B-VACN_B =5.12 mV, IADPT_GAIN = 0 | –25% | 10% | ||||
CIADPT_MAX | Maximum capacitance at IADPT Pin | 100 | pF | |||
VIBAT_CLAMP | IBAT output clamp voltage | 3.1 | 3.2 | 3.3 | V | |
IIBAT | IBAT output current | 1 | 2.5 | mA | ||
AIBAT | Charge and discharge current sensing gain on IBAT pin | V(IBAT) / V(SRN-SRP), IBAT_GAIN = 0, | 8 | V/V | ||
V(IBAT) / V(SRN-SRP), IBAT_GAIN = 1, | 64 | V/V | ||||
IIBAT_CHG_ACC | Charge and discharge current monitor accuracy on IBAT pin | VSRN-VSRP= 61.44 mV, IBAT_GAIN=0b | –1.5% | 2% | ||
VSRN-VSRP= 40.96 mV, IBAT_GAIN=0b | –2% | 3% | ||||
VSRN-VSRP= 20.48 mV, IBAT_GAIN=0b | –3% | 7% | ||||
VSRN-VSRP= 10.24 mV, IBAT_GAIN=0b | –6% | 13% | ||||
VSRN-VSRP= 5.12 mV, IBAT_GAIN=0b | –12% | 27% | ||||
CIBAT_MAX | Maximum capacitance at IBAT Pin | 100 | pF | |||
SYSTEM POWER SENSE AMPLIFIER | ||||||
VPSYS | PSYS output voltage range | 0 | 3.3 | V | ||
IPSYS | PSYS output current | 0 | 260.00 | µA | ||
APSYS | PSYS system gain | I(PSYS) / (P(IN) +P(BAT)), PSYS_CONFIG =00b;PSYS_RATIO =1b | 1 | µA/W | ||
VPSYS_ACC_ADPT | PSYS gain accuracy (PSYS_CONFIG = 00b) | Adapter only monitor system power: VBUS= 28 V IBUS=3.6A (100W), TA = 0 to 85°C, PSYS_RATIO=1b, RAC=10mΩ, RSR=5mΩ. | –3% | 4.5% | ||
VPSYS_ACC_BAT | PSYS gain accuracy (PSYS_CONFIG = 00b) | Battery only monitor system power: VBAT= 11.1 V IBAT=9.1A (100W), TA = 0 to 85°C, PSYS_RATIO=1b, RAC=10mΩ, RSR=5mΩ. | –3.5% | 2% | ||
VPSYS_CLAMP | PSYS clamp voltage | 3.1 | 3.3 | V | ||
INTEGRATED ANALOG TO DIGITAL CONVERSION (ADC) | ||||||
ADCRES | ADC Effective resolution | ADC_SAMPLE[1:0]=00b | 14 | 15 | bits | |
ADCRES | ADC Effective resolution | ADC_SAMPLE[1:0]=01b | 13 | 14 | bits | |
ADCRES | ADC Effective resolution | ADC_SAMPLE[1:0]=10b | 12 | 13 | bits | |
ADC_VBUS | ADC Input voltage reading at ADC_VBUS() register | Range | 0 | 65534 | mV | |
LSB | 2 | mV | ||||
Accuracy at VIN=28V | –2 | 2 | % | |||
ADC_IIN | ADC Input voltage reading at ADC_IIN() register | Range | –16383.5 | 16383.5 | mA | |
LSB based on 10mohm RAC | 0.5 | mA | ||||
Accuracy at VACP_A-VACN_A+VACP_B-VACN_B = 50 mV | –4 | 2.5 | % | |||
ADC_VSYS | ADC Input voltage reading at ADC_VSYS() register | Range | 0 | 65534 | mV | |
LSB | 2 | mV | ||||
Accuracy at VSYS=9V | –2 | 2 | % | |||
ADC_VBAT | ADC Input voltage reading at ADC_VBAT() register | Range | 0 | 32767 | mV | |
LSB | 1 | mV | ||||
Accuracy at VBAT=9V | –2 | 1 | % | |||
ADC_PSYS | ADC Input voltage reading at ADC_PSYS() register | Range | 0 | 4095 | mV | |
LSB | 1 | mV | ||||
Accuracy at V_PSYS=2V | –2 | 2 | % | |||
ADC_CMPIN_TR | ADC Input voltage reading at ADC_CMPIN_TR() register | Range | 0 | 4095 | mV | |
LSB | 1 | mV | ||||
Accuracy at V_CMPIN_TR=2V | –2 | 2 | % | |||
CMPIN_TR PIN Voltage under TEMPERATURE REGULATION(TREG) | ||||||
VTREG | CMPIN_TR pin voltage under temperature regulation | 1.200 | V | |||
VTREG_ACC | CMPIN_TR pin voltage accuracy under temperature regulation | –2.0% | 2.0% | |||
VTREG_PP | TREG PROCHOT PROFILE thereshold level | 1.07 | 1.100 | 1.13 | V | |
SLEEP COMPARATOR FOR FORWARD MODE BETWEEN VBUS and ACP_A(SC_VBUSACP) | ||||||
VSC_VBUSACP_rising | VBUS-ACP_A rising threshold for sleep comparator to shut down converter when Efuse/PFET is not fully on | 700 | 850 | 1000 | mV | |
VSC_VBUSACP_falling | VBUS-ACP_A falling threshold for sleep comparator to recover converter swithcing after Efuse/PFET is fully on | 650 | 800 | 950 | mV | |
HIGH DUTY BUCK EXIT COMPARATOR (HDBCP) | ||||||
VHDBCP_VSYS_RISE | VSYS rising/ VBUS falling threshold for comparator to exit high duty buck mode by forcing HIGH_DUTY_BUCK=0b | 97.2% | 97.7% | 98.2% | ||
VHDBCP_HYS | Hystersis when VSYS falling/VBUS rising based on 97.5%*VBUS threshold to allow writing HIGH_DUTY_BUCK bit to 1b | 200.0 | mV | |||
tHDBCP_VSYS_DEG | Comparator deglitch time for both rising and falling edge | 15.0 | us | |||
VMIN ACTIVE PROTECTION(VAP) PROCHOT COMPARATOR | ||||||
VSYS_TH1Z | VAP VSYS rising threshold 1 | VSYS_TH1()=001110b | 6.4 | 6.55 | 6.7 | V |
VSYS_TH1 | VAP VSYS falling threshold 1 | VSYS_TH1()=001110b | 6.25 | 6.4 | 6.55 | V |
VSYS_TH1_HYST | VAP VSYS threshold 1 hysteresis | 150 | mV | |||
VSYS_TH2Z | VAP VSYS rising threshold 2 | VSYS_TH2()=001001b | 5.9 | 6.05 | 6.20 | V |
VSYS_TH2 | VAP VSYS falling threshold 2 | VSYS_TH2()=001001b | 5.75 | 5.9 | 6.05 | V |
VSYS_TH2_HYST | VAP VSYS threshold 2 hysteresis | 150 | mV | |||
VBUS_VAP_THZ | Convervative VAP VBUS rising threshold | VBUS_VAP_TH()=0000000b | 3.35 | 3.5 | 3.65 | V |
VBUS_VAP_TH | Convervative VAP VBUS falling threshold | VBUS_VAP_TH()=0000000b | 3.05 | 3.2 | 3.35 | V |
VBUS_VAP_TH_HYST | Convervative VAP VBUS threshold hysteresis | 300 | mV | |||
PEAK POWER MODE LEVEL2 ADAPTER CURRENT LIMIT(ILIM2) | ||||||
ILIM2_VTH | Based on percentage of IINDPM(ILIM1) level | ILIM2_VTH=01001b | 150% | |||
VILIM2_CEILING | ILIM2 high clamp based on dual phase total input current sense voltage ACP_A -ACN_A +ACP_B -ACN_B | Set IIN_HOST() to maximum, and ILIM2_VTH=11110b | 240 | 258 | 275 | mV |
PEAK POWER MODE SYSTEM VOLTAGE SAG COMPARATOR(SYS_SAG) | ||||||
VSYS_SAG | VSYS undershoot comparator threshold to trigger peak power mode ILIM2 as percentage of VSYS_MIN() | EN_PKPWR_VSYS=1b | 91.4% | 93.25% | 95.0% | |
VSYS_SAG_HYST | VSYS undervoltage hysteresis | 100 | mV | |||
VSYS UNDER VOLTAGE PROTECTION COMPARATOR(VSYS_UVP) | ||||||
VSYS_UVLOZ | VSYS undervoltage rising threshold | VSYS rising | 2.35 | 2.55 | 2.75 | V |
VSYS_UVLO | VSYS undervoltage falling threshold | VSYS falling VSYS_UVP()=000b | 2.2 | 2.4 | 2.6 | V |
VSYS_UVLOZ | VSYS undervoltage rising threshold | VSYS rising | 4.75 | 4.95 | 5.15 | V |
VSYS_UVLO | VSYS undervoltage falling threshold | VSYS falling VSYS_UVP()=011b | 4.6 | 4.8 | 5.0 | V |
VSYS_UVLOZ | VSYS undervoltage rising threshold | VSYS rising | 7.15 | 7.35 | 7.55 | V |
VSYS_UVLO | VSYS undervoltage falling threshold | VSYS falling VSYS_UVP()=110b | 7.0 | 7.2 | 7.4 | V |
VBUS UNDER VOLTAGE LOCKOUT COMPARATOR(VBUS_UVLO) | ||||||
VVBUS_UVLOZ | VBUS undervoltage rising threshold | VBUS rising | 2.5 | 2.7 | 2.9 | V |
VVBUS_UVLO | VBUS undervoltage falling threshold | VBUS falling | 2.3 | 2.6 | 2.8 | V |
VVBUS_CONVEN | VBUS converter enable rising threshold | VBUS rising | 3.1 | 3.4 | 3.7 | V |
VVBUS_CONVENZ | VBUS converter enable falling threshold | VBUS falling | 2.9 | 3.2 | 3.5 | V |
VBAT UNDER VOLTAGE LOCKOUT COMPARATOR(VBAT_UVLO) | ||||||
VVBAT_UVLOZ | VBAT undervoltage rising threshold | VSRN rising | 3.5 | 3.95 | 4.25 | V |
VVBAT_UVLO | VBAT undervoltage falling threshold | VSRN falling | 3.3 | 3.75 | 4.05 | V |
VVBAT_UVLO_HYST | VBAT undervoltage hysteresis | 200 | mV | |||
VVBAT_OTGEN | VBAT OTG enable rising threshold | VSRN rising | 4.80 | 5.0 | 5.20 | V |
VVBAT_OTGENZ | VBAT OTG enable falling threshold | VSRN falling | 4.45 | 4.65 | 4.85 | V |
VVBAT_OTGEN_HYST | VBAT OTG enable hysteresis | 350 | mV | |||
VBUS UNDER VOLTAGE PROTECTION COMPARATOR (OTG MODE) | ||||||
VVBUS_OTG_UV | VBUS undervoltage falling threshold | As percentage of OTG_VOLTAGE() setting | 65% | 75% | 85% | |
VVBUS_OTG_UVZ | VBUS undervoltage rising threshold hysteresis based on falling threshold | 100 | mV | |||
VBUS OVER VOLTAGE PROTECTION COMPARATOR (OTG MODE) | ||||||
VVBUS_OTG_OV | VBUS overvoltage rising threshold | As percentage of OTG_VOLTAGE() setting= 12V | 110% | 118% | 125% | |
VVBUS_OTG_OVZ | VBUS overvoltage falling threshold | As percentage of OTG_VOLTAGE() setting= 12V | 100% | 105% | 110% | |
PRE-CHARGE to FAST CHARGE COMPARATOR | ||||||
VBAT_PRECHG_Z | VBAT rising threshold | VBAT rising as negative offset of VSYS_MIN() | -150 | 50 | 200 | mV |
VBAT_PRECHG | VBAT falling threshold | VBAT falling as negative offset of VSYS_MIN() | -50 | 150 | 300 | mV |
VBAT_PRECHG_HYST | VBAT hysterisis | 100 | mV | |||
TRICKLE CHARGE to PRE-CHARGE TRANSITION | ||||||
VBAT_SHORT_Z | VBAT short rising threshold | VBAT rising | 2.9 | 3.0 | 3.1 | V |
VBAT_SHORT | VBAT short falling threshold | VBAT falling | 2.80 | 2.9 | 3.0 | V |
VBAT_SHORT_HYST | VBAT short hysteresis | 100.0 | mV | |||
IBAT_SHORT | VBAT short trickle charge current maximum clamp | 128.0 | mA | |||
INPUT OVER-VOLTAGE COMPARATOR (ACOV) | ||||||
VACOV_RISE_15SPR | VBUS overvoltage rising threshold for 15V SPR | VBUS rising(ACOV_ADJ=00b) | 19.25 | 20.00 | 20.75 | V |
VACOV_FALL_15SPR | VBUS overvoltage falling threshold 15V SPR | VBUS falling(ACOV_ADJ=00b) | 18.25 | 19.00 | 19.75 | V |
VACOV_RISE_20SPR | VBUS overvoltage rising threshold 20V SPR | VBUS rising(ACOV_ADJ=01b) | 26.25 | 27.00 | 27.75 | V |
VACOV_FALL_20SPR | VBUS overvoltage falling threshold 20V SPR | VBUS falling(ACOV_ADJ=01b) | 25.25 | 26.00 | 26.75 | V |
VACOV_RISE_28EPR | VBUS overvoltage rising threshold 28V EPR | VBUS rising(ACOV_ADJ=10b Default) | 32.25 | 33.00 | 33.75 | V |
VACOV_FALL_28EPR | VBUS overvoltage falling threshold 28V EPR | VBUS falling(ACOV_ADJ=10b Default) | 31.25 | 32.00 | 32.75 | V |
VACOV_RISE_36EPR | VBUS overvoltage rising threshold 36V EPR | VBUS rising(ACOV_ADJ=11b) | 40.25 | 41.00 | 41.75 | V |
VACOV_FALL_36EPR | VBUS overvoltage falling threshold 36V EPR | VBUS falling(ACOV_ADJ=11b) | 39.25 | 40.00 | 40.75 | V |
VACOV_HYST | VBUS overvoltage hysteresis | 1.00 | V | |||
INPUT OVER CURRENT COMPARATOR (ACOC) | ||||||
VACOC | ACP to ACN rising threshold, w.r.t. ILIM2 in REG0x33[15:11] | Voltage across input sense resistor rising, Reg0x31[2] = 1 | 170 | 200 | 230 | % |
VACOC_FLOOR | ACOC low clamp based on dual phase total input current sense ACP_A -ACN_A +ACP_B -ACN_B | Set IIN_HOST() to minimum | 46 | 50 | 54 | mV |
VACOC_CEILING | ACOC high clamp based on dual phase total input current sense ACP_A -ACN_A +ACP_B -ACN_B | Set IIN_HOST() to maximum | 174 | 180 | 184 | mV |
SYSTEM OVER-VOLTAGE COMPARATOR (SYSOVP) | ||||||
VSYSOVP_RISE | System overvoltage rising threshold to turn off converter | 2 s | 11.85 | 12.15 | 12.35 | V |
3 s | 16.8 | 17.15 | 17.4 | V | ||
4 s | 21.90 | 22.3 | 22.60 | V | ||
5 s | 26.90 | 27.3 | 27.70 | V | ||
VSYSOVP_FALL | System overvoltage falling threshold | 2 s | 11.6 | V | ||
3 s | 16.60 | V | ||||
4 s | 21.7 | V | ||||
5 s | 26.80 | V | ||||
ISYSOVP | Discharge current during SYSOVP | Through VSYS pin | 20 | mA | ||
BAT OVER-VOLTAGE COMPARATOR (BATOVP) | ||||||
VBATOVP_RISE | Overvoltage rising threshold as percentage of CHARGE_VOLTAGE() | 2 s - 5 s | 107.8% | 108.8% | 109.6% | |
VBATOVP_FALL | Overvoltage falling threshold as percentage of CHARGE_VOLTAGE() | 2 s - 5 s | 104.4% | 105.5% | 106.5% | |
VBATOVP_HYST | Overvoltage hysteresis as percentage of CHARGE_VOLTAGE() | 2 s - 5 s | 3.3% | |||
IBATOVP | Discharge current during BATOVP | Through VSYS pin | 20 | mA | ||
CONVERTER OVER-CURRENT COMPARATOR (OCP_SW2) | ||||||
VOCP_LIMIT_SW2 | Converter Over-Current Limit through Q4 VDS | OCP_SW2_HIGH_RANGE=0 | 150 | mV | ||
OCP_SW2_HIGH_RANGE=1 | 260 | mV | ||||
VOCP_LIMIT__SYSSHORT_SW2 | Under OTG_UVP, Converter Over-Current Limit through and Q4 VDS | OCP_SW2_HIGH_RANGE=0 | 90 | mV | ||
OCP_SW2_HIGH_RANGE=1 | 150 | mV | ||||
CONVERTER OVER-CURRENT COMPARATOR (OCP_SW1X) | ||||||
VOCP_LIMIT_SW1X_RAC | Converter Over-Current Limit through RAC | OCP_SW1X_HIGH_RANGE=0 | 150 | mV | ||
OCP_SW1X_HIGH_RANGE=1 | 260 | mV | ||||
VOCP_LIMIT_SYSSHORT_SW1X_RAC | Under SYS_UVP, Converter Over-Current Limit through RAC | OCP_SW1X_HIGH_RANGE=0 | 90 | mV | ||
OCP_SW1X_HIGH_RANGE=1 | 150 | mV | ||||
THERMAL SHUTDOWN COMPARATOR | ||||||
TSHUT_RISE | Thermal shutdown rising temperature | Temperature increasing | 155 | °C | ||
TSHUT_FALL | Thermal shutdown falling temperature | Temperature reducing | 135 | °C | ||
TSHUT_HYS | Thermal shutdown hysteresis | 20 | °C | |||
ICRIT PROCHOT COMPARATOR | ||||||
VICRIT_PRO | Input current rising threshold for throttling as 10% above ILIM2_VTH() | Only when ILIM2 setting is higher than 4A | 104.5% | 110% | 117.5% | |
INOM PROCHOT COMPARATOR | ||||||
VINOM_PRO | INOM rising threshold as 10% above IIN_DPM() and EN_EXTILIM=0b | Accuracy is ensured only when IIN_DPM() is 2A or higher. There is minimum clamp at 500mA. Accuracy between 500mA and 2A may be impaired. | 104% | 110% | 117% | |
BATTERY DISCHARGE CURRENT LIMIT PROCHOT COMPARATOR(IDCHG_TH1 and IDCHG_TH2) | ||||||
IDCHG_TH1 | IDCHG threshold1 voltage across SRN and SRP pins for throttling CPU | IDCHG_TH1()=010000b | 47.5 | mV | ||
–3.0% | 3.2% | |||||
IDCHG_DGLT1 | IDCHG threshold1 deglitch time | IDCHG_DEG1()=01b | 1.25 | sec | ||
IDCHG_TH2 | IDCHG threshold2 voltage across SRN and SRP pins | IDCHG_TH1()=010000b, IDCHG_TH2()=001b | 71.25 | mV | ||
–3.0% | 3.2% | |||||
IDCHG_DGLT2 | IDCHG threshold2 deglitch time | IDCHG_DEG2()=01b | 1.6 | ms | ||
INDEPENDENT COMPARATOR | ||||||
VINDEP_CMP | Independent comparator threshold | Comparator CMPIN_TR threshold to trigger CMPOUT pulling down, Negative polarity CMP_POL=0b. | 1.18 | 1.2 | 1.23 | V |
VINDEP_CMP_HYS | Independent comparator hysteresis | Comparator CMPIN_TR hysterisis threshold | 100 | mV | ||
PWM OSCILLATOR AND RAMP | ||||||
FSW | PWM switching frequency | PWM_FREQ= 0 | 690 | 770 | 850 | kHz |
FSW | PWM switching frequency | PWM_FREQ= 1 | 540 | 600 | 660 | kHz |
BATFET GATE DRIVER (BATDRV for NFET) | ||||||
VBATDRV_ON | Gate drive voltage on NMOS BATFET | 4.70 | 5.00 | 5.40 | V | |
VBATDRV_SUPPLEMENT | BATFET Source-Drain voltage during ideal diode regulation under supplement mode | 30.00 | mV | |||
IBATDRV_ON | BATDRV on, VBATDRV=VBAT+2V | 30 | 40 | µA | ||
IBATDRV_OFF | BATDRV off, BATDRV=VBAT+2V | 0.54 | 0.85 | mA | ||
PWM HIGH SIDE DRIVER (HIDRV1_A for Q1_A, HIDRV1_B for Q1_B) | ||||||
RDS_HI_ON_Q1 | High side driver (HSD) turn on resistance | VBTST1 - VSW1 = 4.5 V | 1.00 | Ω | ||
RDS_HI_OFF_Q1 | High side driver turn off resistance | VBTST1 - VSW1 = 4.5 V | 0.4 | 0.6 | Ω | |
VBTST1_REFRESH | Bootstrap refresh comparator falling threshold voltage | VBTST1 - VSW1 when low side refresh pulse is requested | 3.0 | 3.3 | 3.6 | V |
PWM LOW SIDE DRIVER (LODRV1_A for Q2_A, LODRV1_B for Q2_B) | ||||||
RDS_LO_ON_Q2 | Low side driver (LSD) turn on resistance | VBTST1 - VSW1 = 4.5 V | 1.0 | Ω | ||
RDS_LO_OFF_Q2 | Low side driver turn off resistance | VBTST1 - VSW1 = 4.5 V | 0.4 | 0.6 | Ω | |
PWM HIGH SIDE DRIVER (HIDRV2 for Q4) | ||||||
RDS_HI_ON_Q4 | High side driver (HSD) turn on resistance | VBTST2 - VSW2 = 4.5 V | 1.50 | Ω | ||
RDS_HI_OFF_Q4 | High side driver turn off resistance | VBTST2 - VSW2 = 4.5 V | 0.50 | 0.80 | Ω | |
VBTST2_REFRESH | Bootstrap refresh comparator falling threshold voltage | VBTST2 - VSW2 when low side refresh pulse is requested | 3.0 | 3.3 | 3.6 | V |
PWM LOW SIDE DRIVER (LODRV2 for Q3) | ||||||
RDS_LO_ON_Q3 | Low side driver (LSD) turn on resistance | VBTST2 - VSW2 = 4.5 V | 1.10 | Ω | ||
RDS_LO_OFF_Q3 | Low side driver turn off resistance | VBTST2 - VSW2 = 4.5 V | 0.40 | 0.70 | Ω | |
INTERNAL SOFT START During Charge Enable | ||||||
SSSTEP_DAC | Soft Start Step Size | 8 | mA | |||
INTEGRATED BTST DIODE (D1_X) | ||||||
VF_D1 | Forward bias voltage | IF = 20 mA at 25°C | 0.8 | V | ||
INTEGRATED BTST DIODE (D2) | ||||||
VF_D2 | Forward bias voltage | IF = 20 mA at 25°C | 0.8 | V | ||
INTERFACE | ||||||
LOGIC INPUT (SDA, SCL, EN_OTG) | ||||||
VIN_ LO_EN_OTG | Input low level for EN_OTG pin | 0.8 | V | |||
VIN_ HI_EN_OTG | Input high level for EN_OTG pin | 1.35 | V | |||
VIN_ LO | Input low level for SCL/SDA | I2C (1.2V~5V VDD Pullup) | 0.42 | V | ||
VIN_ HI | Input high level for SCL/SDA | I2C (1.2V~5V VDD Pullup) | 0.8 | V | ||
LOGIC OUTPUT OPEN DRAIN SDA | ||||||
VOUT_ LO_SDA | Output Saturation Voltage | 5 mA drain current | 0.3 | V | ||
VOUT_ LEAK_SDA | Leakage Current | V = 5.5V | –1 | 1 | µA | |
LOGIC OUTPUT OPEN DRAIN CHRG_OK | ||||||
VOUT_ LO_CHRG_OK | Output Saturation Voltage | 5 mA drain current | 0.4 | V | ||
VOUT_ LEAK _CHRG_OK | Leakage Current | V = 5.5V | –1 | 1 | µA | |
LOGIC OUTPUT OPEN DRAIN CMPOUT | ||||||
VOUT_ LO_CMPOUT | Output Saturation Voltage | 5 mA drain current | 0.4 | V | ||
VOUT_ LEAK _CMPOUT | Leakage Current | V = 5.5V | –1 | 1 | µA | |
LOGIC OUTPUT OPEN DRAIN (PROCHOT) | ||||||
VOUT_ LO_PROCHOT | Output saturation voltage | 50 Ω pullup to 1.05 V / 5-mA | 0.4 | V | ||
VOUT_ LEAK_PROCHOT | Leakage current | V = 5.5 V | –1 | 1 | µA | |
ANALOG INPUT (ILIM_HIZ) | ||||||
VHIZ_ LOW | Voltage to get out of HIZ mode | ILIM_HIZ pin rising | 0.7 | 0.8 | V | |
VHIZ_ HIGH | Voltage to enable HIZ mode | ILIM_HIZ pin falling | 0.4 | 0.5 | V | |
VILIM_ENZ | Voltage to disable external current limit function on ILIM_HIZ pin (EN_EXTLIM=1b) | ILIM_HIZ pin rising | 4.1 | 4.2 | V | |
VILIM_EN | Voltage to enable external current limit function on ILIM_HIZ pin (EN_EXTLIM=1b) | ILIM_HIZ pin falling | 3.9 | 4.0 | V | |
ANALOG INPUT (CELL_BATPRES) | ||||||
VCELL_5S | 5S | CELL_BATPRES pin voltage as percentage of REGN = 5 V | 90.0% | 100.0% | ||
VCELL_4S | 4S | CELL_BATPRES pin voltage as percentage of REGN = 5 V | 68.4% | 75.0% | 81.5% | |
VCELL_3S | 3S | CELL_BATPRES pin voltage as percentage of REGN = 5 V | 51.7% | 55.0% | 65.0% | |
VCELL_2S | 2S | CELL_BATPRES pin voltage as percentage of REGN = 5 V | 18.4% | 40.0% | 48.5% | |
VCELL_BATPRES_RISE | Battery is present | CELL_BATPRES rising | 18.0% | |||
VCELL_BATPRES_FALL | Battery is removed | CELL_BATPRES falling | 14.7% |