SLUSFH5A May   2024  – October 2024 BQ25856-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Power-On-Reset
      2. 7.3.2  Device Power-Up From Battery Without Input Source
      3. 7.3.3  Device Power Up From Input Source
        1. 7.3.3.1 VAC Operating Window Programming (ACUV and ACOV)
        2. 7.3.3.2 REGN Regulator (REGN LDO)
        3. 7.3.3.3 Compensation-Free Buck-Boost Converter Operation
          1. 7.3.3.3.1 Light-Load Operation
        4. 7.3.3.4 Switching Frequency and Synchronization (FSW_SYNC)
        5. 7.3.3.5 Device HIZ Mode
      4. 7.3.4  Battery Charging Management
        1. 7.3.4.1 Autonomous Charging Cycle
          1. 7.3.4.1.1 Charge Current Programming (ICHG pin and ICHG_REG)
        2. 7.3.4.2 Li-Ion Battery Charging Profile
        3. 7.3.4.3 LiFePO4 Battery Charging Profile
        4. 7.3.4.4 Charging Termination for Li-ion and LiFePO4
        5. 7.3.4.5 Charging Safety Timer
        6. 7.3.4.6 Thermistor Qualification
          1. 7.3.4.6.1 JEITA Guideline Compliance in Charge Mode
          2. 7.3.4.6.2 Cold/Hot Temperature Window in Reverse Mode
      5. 7.3.5  Power Management
        1. 7.3.5.1 Dynamic Power Management: Input Voltage and Input Current Regulation
          1. 7.3.5.1.1 Input Current Regulation
            1. 7.3.5.1.1.1 ILIM_HIZ Pin
          2. 7.3.5.1.2 Input Voltage Regulation
      6. 7.3.6  Switching Frequency Dithering Feature
      7. 7.3.7  Reverse Mode Power Direction
        1. 7.3.7.1 Auto Reverse Mode
      8. 7.3.8  Integrated 16-Bit ADC for Monitoring
      9. 7.3.9  Status Outputs (PG, STAT1, STAT2, and INT)
        1. 7.3.9.1 Power Good Indicator (PG)
        2. 7.3.9.2 Charging Status Indicator (STAT1, STAT2 Pins)
        3. 7.3.9.3 Interrupt to Host (INT)
      10. 7.3.10 Protections
        1. 7.3.10.1 Voltage and Current Monitoring
          1. 7.3.10.1.1 VAC Over-voltage Protection (VAC_OVP)
          2. 7.3.10.1.2 VAC Under-voltage Protection (VAC_UVP)
          3. 7.3.10.1.3 Battery Over-voltage Protection (BAT_OVP)
          4. 7.3.10.1.4 Battery Over-current Protection (BAT_OCP)
          5. 7.3.10.1.5 Reverse Mode Over-voltage Protection (REV_OVP)
          6. 7.3.10.1.6 Reverse Mode Under-voltage Protection (REV_UVP)
          7. 7.3.10.1.7 DRV_SUP Under-voltage and Over-voltage Protection (DRV_OKZ)
          8. 7.3.10.1.8 REGN Under-voltage Protection (REGN_OKZ)
        2. 7.3.10.2 Thermal Shutdown (TSHUT)
      11. 7.3.11 Serial Interface
        1. 7.3.11.1 Data Validity
        2. 7.3.11.2 START and STOP Conditions
        3. 7.3.11.3 Byte Format
        4. 7.3.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.3.11.5 Target Address and Data Direction Bit
        6. 7.3.11.6 Single Write and Read
        7. 7.3.11.7 Multi-Write and Multi-Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host Mode and Default Mode
      2. 7.4.2 Register Bit Reset
    5. 7.5 BQ25856-Q1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 ACUV / ACOV Input Voltage Operating Window Programming
          2. 8.2.1.2.2 Charge Voltage Selection
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Inductor Selection
          5. 8.2.1.2.5 Input (VAC) Capacitor
          6. 8.2.1.2.6 Output (VBAT) Capacitor
          7. 8.2.1.2.7 Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
          8. 8.2.1.2.8 Power MOSFETs Selection
          9. 8.2.1.2.9 Converter Fast Transient Response
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application (4s LiFePO4 car battery configuration)
        1. 8.2.2.1 Design Requirements
      3. 8.2.3 Typical Application (Capacitor Backup)
        1. 8.2.3.1 Design Requirements
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RRV|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.1.2.9 Converter Fast Transient Response

The device integrates all the loop compensation, thereby providing a high density solution with ease of use. For faster transient reponse in reverse operating mode, the EN_CONV_FAST_TRANSIENT bit can be set to 1. If device is not used in reverse boost mode operation, this section can be disregarded.

When the converter is operating in boost mode, the non-continuous inductor current flow to the load results in a right-half plane (RHP) zero. The RHP zero location is:

Equation 36. RHPz=VIN,boostIIN,boost12πL

For good phase margin, the unity gain bandwidth (UGBW) of the converter should be about 1/3 of the RHPz. The boost output capacitor (Cload), and the converter transient parameters (R1, gm1) need to be scaled to move the location of the UGBW of the converter.

Equation 37. 1≈Adiv×gm1(sR1C1+1)sC1ViIo×50m11+sCloadRload2

The device adjusts Adiv, gm1 and R1 based on the output voltage and the EN_CONV_FAST_TRANSIENT bit setting per the table below. During some boost case scenarios, the Cload needs to be adjusted to limit the converter bandwidth.

BOOST OUTPUT VOLTAGE Adiv C1 EN_CONV_FAST_TRANSIENT = 0 EN_CONV_FAST_TRANSIENT = 1
gm1 R1 gm1 R1
≤8 V 1/5 75 pF 0.4 μ 600 kΩ 2 μ 1.3 MΩ
8 V to 16 V 1/10 75 pF 0.47 μ 1 MΩ 2 μ 1.8 MΩ
16 V to 32 V 1/20 75 pF 0.67 μ 2.8 MΩ 2 μ 2.8 MΩ
>32 V 1/40 75 pF 2 μ 2.8 MΩ 2 μ 2.8 MΩ

As an example, assume the device operates in reverse boost mode from a 5V supply to provide a 7V boost output voltage with load up-to 5A and 10μH inductor. The RHPz is approximately located at:

Equation 38. RHPz=VIN,boostIIN,boost12πL=11.4kHz

For best stability, the UGBW of the converter should be limited to 1/3 of the RHP zero, or 3.8kHz. If EN_CONV_FAST_TRANSIENT = 1, the equation becomes:

Equation 39. 1≈0.2×2μ (jω×1.3MΩ×75pF+1)jω×75pF5V5A×50m11+jωCload×1.42

Solving the above for Cload gives ≥674 μF capacitor requirement.

Conversely, if EN_CONV_FAST_TRANSIENT = 0, the UGBW equation becomes:

Equation 40. 1≈0.2×0.4μ (jω×0.6MΩ×75pF+1)jω×75pF5V5A×50m11+jωCload×1.42

Solving the above for Cload gives ≥51 μF capacitor requirement. However, the minimum recommended capacitor for converter stability is 80 μF, so this minimum value should be used.