SLUSFH5A May   2024  – October 2024 BQ25856-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Power-On-Reset
      2. 7.3.2  Device Power-Up From Battery Without Input Source
      3. 7.3.3  Device Power Up From Input Source
        1. 7.3.3.1 VAC Operating Window Programming (ACUV and ACOV)
        2. 7.3.3.2 REGN Regulator (REGN LDO)
        3. 7.3.3.3 Compensation-Free Buck-Boost Converter Operation
          1. 7.3.3.3.1 Light-Load Operation
        4. 7.3.3.4 Switching Frequency and Synchronization (FSW_SYNC)
        5. 7.3.3.5 Device HIZ Mode
      4. 7.3.4  Battery Charging Management
        1. 7.3.4.1 Autonomous Charging Cycle
          1. 7.3.4.1.1 Charge Current Programming (ICHG pin and ICHG_REG)
        2. 7.3.4.2 Li-Ion Battery Charging Profile
        3. 7.3.4.3 LiFePO4 Battery Charging Profile
        4. 7.3.4.4 Charging Termination for Li-ion and LiFePO4
        5. 7.3.4.5 Charging Safety Timer
        6. 7.3.4.6 Thermistor Qualification
          1. 7.3.4.6.1 JEITA Guideline Compliance in Charge Mode
          2. 7.3.4.6.2 Cold/Hot Temperature Window in Reverse Mode
      5. 7.3.5  Power Management
        1. 7.3.5.1 Dynamic Power Management: Input Voltage and Input Current Regulation
          1. 7.3.5.1.1 Input Current Regulation
            1. 7.3.5.1.1.1 ILIM_HIZ Pin
          2. 7.3.5.1.2 Input Voltage Regulation
      6. 7.3.6  Switching Frequency Dithering Feature
      7. 7.3.7  Reverse Mode Power Direction
        1. 7.3.7.1 Auto Reverse Mode
      8. 7.3.8  Integrated 16-Bit ADC for Monitoring
      9. 7.3.9  Status Outputs (PG, STAT1, STAT2, and INT)
        1. 7.3.9.1 Power Good Indicator (PG)
        2. 7.3.9.2 Charging Status Indicator (STAT1, STAT2 Pins)
        3. 7.3.9.3 Interrupt to Host (INT)
      10. 7.3.10 Protections
        1. 7.3.10.1 Voltage and Current Monitoring
          1. 7.3.10.1.1 VAC Over-voltage Protection (VAC_OVP)
          2. 7.3.10.1.2 VAC Under-voltage Protection (VAC_UVP)
          3. 7.3.10.1.3 Battery Over-voltage Protection (BAT_OVP)
          4. 7.3.10.1.4 Battery Over-current Protection (BAT_OCP)
          5. 7.3.10.1.5 Reverse Mode Over-voltage Protection (REV_OVP)
          6. 7.3.10.1.6 Reverse Mode Under-voltage Protection (REV_UVP)
          7. 7.3.10.1.7 DRV_SUP Under-voltage and Over-voltage Protection (DRV_OKZ)
          8. 7.3.10.1.8 REGN Under-voltage Protection (REGN_OKZ)
        2. 7.3.10.2 Thermal Shutdown (TSHUT)
      11. 7.3.11 Serial Interface
        1. 7.3.11.1 Data Validity
        2. 7.3.11.2 START and STOP Conditions
        3. 7.3.11.3 Byte Format
        4. 7.3.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.3.11.5 Target Address and Data Direction Bit
        6. 7.3.11.6 Single Write and Read
        7. 7.3.11.7 Multi-Write and Multi-Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host Mode and Default Mode
      2. 7.4.2 Register Bit Reset
    5. 7.5 BQ25856-Q1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 ACUV / ACOV Input Voltage Operating Window Programming
          2. 8.2.1.2.2 Charge Voltage Selection
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Inductor Selection
          5. 8.2.1.2.5 Input (VAC) Capacitor
          6. 8.2.1.2.6 Output (VBAT) Capacitor
          7. 8.2.1.2.7 Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
          8. 8.2.1.2.8 Power MOSFETs Selection
          9. 8.2.1.2.9 Converter Fast Transient Response
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application (4s LiFePO4 car battery configuration)
        1. 8.2.2.1 Design Requirements
      3. 8.2.3 Typical Application (Capacitor Backup)
        1. 8.2.3.1 Design Requirements
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RRV|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

Proper layout of the components to minimize high frequency current path loops is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout.

Table 10-1 PCB Layout Guidelines
COMPONENTSFUNCTIONIMPACTGUIDELINES
Buck high side FET, Buck low side FET, input capacitorsBuck input loopHigh frequency noise, ripple, efficiencyThis path forms a high frequency switching loop due to the pulsating current at the input of the buck. Place components on the same side of the board. Minimize loop area to reduce parasitic inductance. Maximize trace width to reduce parasitic resistance. Place input ceramic capacitors close to the switching FETs.
Boost low side FET, boost high side FET, output capacitorsBoost output loopHigh frequency noise, ripple, efficiencyThis path forms a high frequency switching loop due to the pulsating current at the output of the boost. Place components on the same side of the board. Minimize loop area to reduce parasitic inductance. Maximize trace width to reduce parasitic resistance. Place output ceramic capacitors close to the switching FETs.
Sense resistors, switching FETs, inductorCurrent pathEfficiencyThe current path from input to output through the power stage and sense resistors has low impedance. Pay attention to via resistance if they are not on the same side. The number of vias can be estimated as 1- to 2-A per via for a 10-mil via with 1 oz. copper thickness.
Switching FETs, inductorPower stageThermal, efficiencyThe switching FETs and inductor are the components with highest power loss. Allow enough copper area for heat dissipation. Multiple thermal vias can be used to connect more copper layers together and dissipate more heat.
DRV_SUP, BTST1, BTST2 capacitorsSwitching FET gate driveHigh frequency noise, parasitic ringing, gate drive integrityThe DRV_SUP capacitor is used to supply the power to drive the low side FETs. The BTST capacitors are used to drive the high side FETs. It is recommended to place the capacitors as close as possible to the IC.
LODRV1, LODRV2Low side gate driveHigh frequency noise, parasitic ringing, gate drive integrityLODRV1 and LODRV2 supplies the gate drive current to turn on the low side FETs. The return of LODRV1 and LODRV2 is PGND. As current take the path of least impedance, a ground plane close to the low side gate drive traces is recommended. Minimize gate drive length and aim for at least 20-mil gate drive trace width.
HIDRV1, HIDRV2, SW1 (pin trace), SW2 (pin trace)High side gate driveHigh frequency noise, parasitic ringing, gate drive integrityHIDRV1 and HIDRV2 supplies the gate drive current to turn on the high side FETs. The return of HIDRV1 and HIDRV2 are SW1 and SW2, respectively. Route HIDRV1/SW1 and HIDRV2/SW2 pair next to each other to reduce gate drive parasitic inductance. Minimize gate drive length and aim for at least 20-mil gate drive trace width.
Current limit resistors, FSW_SYNC resistor IC programmable settingsRegulation accuracy, switching integrityPin voltage determines the settings for input current limit, output current limit and switching frequency. Ground noise on these could lead to inacuracy. Minimize ground return from these resistors to the IC ground pin.
Input (ACP, ACN) and output (SRP, SRN) current senseCurrent regulationRegulation accuracyUse Kelvin-sensing technique for input and output current sense resistors. Connect the current sense traces to the center of the pads, and run current sense traces as differential pairs, away from switching nodes.
Input (ACUV), and output (FB, VO_SNS) voltage sensingVoltage sense and regulationRegulation accuracyACUV divider sets internal input voltage regulation in forward mode (VACUV_DPM). FB divider sets battery voltage regulation in forward mode (VFB_ACC). Route the top of the divider point to the target regulation location. Avoid routing close to high power switching nodes.
Bypass capacitors Noise filterNoise immunityPlace lowest value capacitors closest to the IC.