SLVSE40C February 2018 – September 2019 BQ25882
PRODUCTION DATA.
REG0F is shown in Figure 52 and described in Table 24.
Return to Summary Table.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Field | ADC_DONE_
FLAG |
IINDPM_FLAG | VINDPM_FLAG | TREG_FLAG | WD_FLAG | RESERVED | RESERVED | CHRG_FLAG |
Bit | Field | Type | Reset by REG_RST | Reset by WATCHDOG | Description | |
---|---|---|---|---|---|---|
7 | ADC_DONE_FLAG | R | Yes | No | ADC Conversion Flag (only 1-shot mode):
0 – Conversion not complete 1 – Conversion complete Note: Always reads 0 in continuos mode |
|
6 | IINDPM_FLAG | R | Yes | No | IINDPM Regulation INT Flag:
0 – Normal 1 – IINDPM signal rising edge detected |
|
5 | VINDPM_FLAG | R | Yes | No | VINDPM regulation INT Flag:
0 – Normal 1 – VINDPM signal rising edge detected |
|
4 | TREG_FLAG | R | Yes | No | IC Temperature Regulation INT Flag:
0 – Normal 1 – TREG signal rising edge detected |
|
3 | WD_FLAG | R | Yes | No | I2C Watchdog INT Flag:
0 – Normal 1 – WD_STAT signal rising edge detected |
|
2 | RESERVED | R | Yes | No | Reserved bit always reads 0 | |
1 | RESERVED | R | Yes | No | Reserved bit always reads 0 | |
0 | CHRG_FLAG | R | Yes | No | Charge Status INT Flag:
0 – Normal 1 – CHRG_STAT[2:0] bits changed (transition to any state) |