SLVSE40C February 2018 – September 2019 BQ25882
PRODUCTION DATA.
REG0B is shown in Figure 48 and described in Table 20.
Return to Summary Table.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset | X | X | X | X | X | X | X | X |
Field | ADC_DONE_
STAT |
IINDPM_STAT | VINDPM_STAT | TREG_STAT | WD_STAT | CHRG_STAT[2:0] |
Bit | Field | Type | Reset by REG_RST | Reset by WATCHDOG | Description | |
---|---|---|---|---|---|---|
7 | ADC_DONE_STAT | R | No | No | ADC Conversion Status (in one-shot mode only):
0 – Conversion not complete 1 – Conversion complete Note: Always reads 0 in continuous mode |
|
6 | IINDPM_STAT | R | No | No | IINDPM Status:
0 – Normal 1 – In IINDPM Regulation (ILIM pin or IINDPM register) |
|
5 | VINDPM_STAT | R | No | No | VINDPM Status:
0 – Normal 1 – In VINDPM Regulation |
|
4 | TREG_STAT | R | No | No | IC Thermal regulation Status:
0 – Normal 1 – In Thermal Regulation |
|
3 | WD_STAT | R | No | No | I2C Watchdog Timer Status bit:
0 – Normal 1 – WD Timer expired |
|
2 | CHRG_STAT[2] | R | No | No | Charge Status bits:
000 – Not Charging 001 – Trickle Charge (VBAT < VBAT_SHORT) 010 – Pre-charge (VBAT_SHORT < VBAT < VBAT_LOWV) 011 – Fast-charge (CC mode) 100 – Taper Charge (CV mode) 101 – Top-off Timer Charging 110 – Charge Termination Done 111 – Reserved |
|
1 | CHRG_STAT[1] | R | No | No | ||
0 | CHRG_STAT[0] | R | No | No |