SLUSC88C March   2015  – October 2022 BQ25895

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  Device Power-On-Reset (POR)
      2. 8.2.2  Device Power Up from Battery without Input Source
      3. 8.2.3  Device Power Up from Input Source
        1. 8.2.3.1 Power Up REGN Regulation (LDO)
        2. 8.2.3.2 Poor Source Qualification
        3. 8.2.3.3 Input Source Type Detection
          1. 8.2.3.3.1 D+/D– Detection Sets Input Current Limit
          2. 8.2.3.3.2 Force Input Current Limit Detection
        4. 8.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.2.3.5 Converter Power-Up
      4. 8.2.4  Input Current Optimizer (ICO)
      5. 8.2.5  Boost Mode Operation from Battery
      6. 8.2.6  Power Path Management
        1. 8.2.6.1 Narrow VDC Architecture
        2. 8.2.6.2 Dynamic Power Management
        3. 8.2.6.3 Supplement Mode
      7. 8.2.7  Battery Charging Management
        1. 8.2.7.1 Autonomous Charging Cycle
        2. 8.2.7.2 Battery Charging Profile
        3. 8.2.7.3 Charging Termination
        4. 8.2.7.4 Resistance Compensation (IRCOMP)
        5. 8.2.7.5 Thermistor Qualification
          1. 8.2.7.5.1 Cold/Hot Temperature Window in Charge Mode
          2. 8.2.7.5.2 Cold/Hot Temperature Window in Boost Mode
        6. 8.2.7.6 Charging Safety Timer
      8. 8.2.8  Battery Monitor
      9. 8.2.9  Status Outputs (STAT, and INT)
        1. 8.2.9.1 Charging Status Indicator (STAT)
        2. 8.2.9.2 Interrupt to Host (INT)
      10. 8.2.10 BATET (Q4) Control
        1. 8.2.10.1 BATFET Disable Mode (Shipping Mode)
        2. 8.2.10.2 BATFET Enable (Exit Shipping Mode)
        3. 8.2.10.3 BATFET Full System Reset
      11. 8.2.11 Current Pulse Control Protocol
      12. 8.2.12 Input Current Limit on ILIM
      13. 8.2.13 Thermal Regulation and Thermal Shutdown
        1. 8.2.13.1 Thermal Protection in Buck Mode
        2. 8.2.13.2 Thermal Protection in Boost Mode
      14. 8.2.14 Voltage and Current Monitoring in Buck and Boost Mode
        1. 8.2.14.1 Voltage and Current Monitoring in Buck Mode
          1. 8.2.14.1.1 Input Overvoltage (ACOV)
          2. 8.2.14.1.2 System Overvoltage Protection (SYSOVP)
        2. 8.2.14.2 Current Monitoring in Boost Mode
          1. 8.2.14.2.1 Boost Mode Overvoltage Protection
      15. 8.2.15 Battery Protection
        1. 8.2.15.1 Battery Overvoltage Protection (BATOVP)
        2. 8.2.15.2 Battery Over-Discharge Protection
        3. 8.2.15.3 System Overcurrent Protection
      16. 8.2.16 Serial Interface
        1. 8.2.16.1 Data Validity
        2. 8.2.16.2 START and STOP Conditions
        3. 8.2.16.3 Byte Format
        4. 8.2.16.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.2.16.5 Target Address and Data Direction Bit
        6. 8.2.16.6 Single Read and Write
        7. 8.2.16.7 Multi-Read and Multi-Write
    3. 8.3 Device Functional Modes
      1. 8.3.1 Host Mode and Default Mode
    4. 8.4 Register Maps
      1. 8.4.1  REG00
      2. 8.4.2  REG01
      3. 8.4.3  REG02
      4. 8.4.4  REG03
      5. 8.4.5  REG04
      6. 8.4.6  REG05
      7. 8.4.7  REG06
      8. 8.4.8  REG07
      9. 8.4.9  REG08
      10. 8.4.10 REG09
      11. 8.4.11 REG0A
      12. 8.4.12 REG0B
      13. 8.4.13 REG0C
      14. 8.4.14 REG0D
      15. 8.4.15 REG0E
      16. 8.4.16 REG0F
      17. 8.4.17 REG10
      18. 8.4.18 REG11
      19. 8.4.19 REG12
      20. 8.4.20 REG13
      21. 8.4.21 REG14
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Buck Input Capacitor
        3. 9.2.2.3 System Output Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Glossary
    6. 12.6 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
QUIESCENT CURRENTS
IBATBattery discharge current (BAT, SW, SYS) in buck modeVBAT = 4.2 V, V(VBUS) < V(UVLO), leakage between BAT and VBUS5µA
High-Z mode, no VBUS, BATFET disabled (REG09[5]=1), battery monitor disabled, TJ < 85°C1223µA
High-Z mode, no VBUS, BATFET enabled (REG09[5]=0), battery monitor disabled, TJ < 85°C3260µA
I(VBUS_HIZ)Input supply current (VBUS) in buck mode when High-Z mode is enabledV(VBUS)= 5 V, High-Z mode, no battery, battery monitor disabled1535µA
V(VBUS)= 12 V, High-Z mode, no battery, battery monitor disabled2550µA
I(VBUS)Input supply current (VBUS) in buck modeVBUS > V(UVLO), VBUS > VBAT, converter not switching1.53mA
VBUS > V(UVLO), VBUS > VBAT, converter switching, VBAT = 3.2 V, ISYS = 0A3mA
VBUS > V(UVLO), VBUS > VBAT, converter switching, VBAT = 3.8 V, ISYS = 0 A3mA
I(BOOST)Battery discharge current in boost modeVBAT = 4.2 V, boost mode, I(VBUS)= 0 A, converter switching5mA
VBUS/BAT POWER UP
V(VBUS_OP)VBUS operating range3.914V
V(VBUS_UVLOZ)VBUS for active I2C, no battery3.6V
V(SLEEP)Sleep mode falling threshold2565120mV
V(SLEEPZ)Sleep mode rising threshold130250370mV
V(ACOV)VBUS over-voltage rising threshold1414.6V
VBUS over-voltage falling threshold13.514V
VBAT(UVLOZ)Battery for active I2C, no VBUS2.3V
VBAT(DPL)Battery depletion falling threshold2.152.5V
VBAT(DPLZ)Battery depletion rising threshold2.352.7V
V(VBUSMIN)Bad adapter detection threshold3.8V
I(BADSRC)Bad adapter detection current source30mA
POWER-PATH MANAGEMENT
VSYSTypical system regulation voltage I(SYS) = 0 A, VBAT> VSYS(MIN), BATFET Disabled (REG09[5]=1)VBAT+
50 mV		V
I(SYS) = 0 A, VBAT< VSYS(MIN), BATFET Disabled (REG09[5]=1)VSYS(MIN) +
150 mV		V
VSYS(MIN)Minimum DC system voltage outputVBAT< VSYS(MIN), SYS_MIN = 3.5 V (REG03[3:1]=101), ISYS= 0 A3.503.65V
VSYS(MAX)Maximum DC system voltage outputVBAT = 4.35 V, SYS_MIN = 3.5V (REG03[3:1]=101), ISYS= 0 A4.404.42V
RON(RBFET)Top reverse blocking MOSFET(RBFET) on-resistance between VBUS and PMIDTJ = –40°C to +85°C2738mΩ
TJ = –40°C to +125°C2744mΩ
RON(HSFET)Top switching MOSFET (HSFET) on-resistance between PMID and SWTJ = –40°C to +85°C2739mΩ
TJ = –40°C to +125°C2747mΩ
RON(LSFET)Bottom switching MOSFET (LSFET) on-resistance between SW and GNDTJ = –40°C to +85°C1624mΩ
TJ = –40°C to +125°C1628mΩ
V(FWD)BATFET forward voltage in supplement modeBAT discharge current 10 mA30mV
VBAT(GD)Battery good comparator rising thresholdVBAT rising3.43.553.7V
VBAT(GD_HYST)Battery good comparator falling thresholdVBAT falling100mV
BATTERY CHARGER
VBAT(REG_RANGE)Typical charge voltage range3.8404.608V
VBAT(REG_STEP)Typical charge voltage step16mV
VBAT(REG)Charge voltage resolution accuracyVBAT = 4.208 V (REG06[7:2]=010111) or
VBAT = 4.352 V (REG06[7:2]=100000)
TJ = –40°C to +85°C		-0.5%0.5%
I(CHG_REG__RANGE)Typical fast charge current regulation range05056mA
I(CHG_REG_STEP)Typical fast charge current regulation step64mA
I(CHG_REG_ACC)Fast charge current regulation accuracyVBAT = 3.1 V or 3.8 V, ICHG = 128 mA
TJ = –40°C to +85°C		-20%20%
VBAT= 3.1 V or 3.8 V, ICHG = 256 mA
TJ = –40°C to +85°C		-10%10%
VBAT= 3.1 V or 3.8 V, ICHG=1792 mA
TJ = –40°C to +85°C		-5%5%
VBAT(LOWV)Battery LOWV falling thresholdFast charge to precharge, BATLOWV (REG06[1]) = 12.62.82.9V
Battery LOWV rising thresholdPrecharge to fast charge, BATLOWV (REG06[1])=1
(Typical 200-mV hysteresis)		2.833.1V
I(PRECHG_RANGE)Precharge current range641024mA
I(PRECHG_STEP)Typical precharge current step64mA
I(PRECHG_ACC)Precharge current accuracyVBAT=2.6 V, IPRECHG = 256 mA–10%+10%
I(TERM_RANGE)Termination current range641024mA
I(TERM_STEP)Typical termination current step64mA
I(TERM_ACC)Termination current accuracyITERM = 256 mA, ICHG<= 1344 mA
TJ = –20°C to +85°C		–12%12%
ITERM = 256 mA, ICHG> 1344 mA
TJ = –20°C to +85°C		–20%20%
V(SHORT)Battery short voltageVBAT falling2V
V(SHORT_HYST)Battery short voltage hysteresisVBAT rising200mV
I(SHORT)Battery short currentVBAT < 2.2 V100mA
V(RECHG)Recharge threshold below VBATREGVBAT falling, VRECHG (REG06[0]=0) = 0100mV
VBAT falling, VRECHG (REG06[0]=0) = 1200mV
IBAT(LOAD)Battery discharge load currentVBAT = 4.2 V15mA
ISYS(LOAD)System discharge load currentVSYS = 4.2 V30mA
RON(BATFET)SYS-BAT MOSFET (BATFET) on-resistanceTJ = 25°C1113mΩ
TJ = –40°C to +125°C1119mΩ
INPUT VOLTAGE / CURRENT REGULATION
VIN(DPM_RANGE)Typical Input voltage regulation range3.915.3V
VIN(DPM_STEP)Typical Input voltage regulation step100mV
VIN(DPM_ACC)Input voltage regulation accuracyVINDPM = 4.4 V, 9 V3%3%
IIN(DPM_RANGE)Typical Input current regulation range1003250mA
IIN(DPM_STEP)Typical Input current regulation step50mA
IIN(DPM100_ACC)Input current 100-mA regulation accuracy
VBAT = 5 V, current pulled from SW		IINLIM (REG00[5:0]) =100 mA8590100mA
IIN(DPM_ACC)Input current regulation accuracy
VBAT = 5 V, current pulled from SW		USB150, IINLIM (REG00[5:0]) = 150 mA125135150mA
USB500, IINLIM (REG00[5:0]) = 500 mA440470500mA
USB900, IINLIM (REG00[5:0]) = 900 mA750825900mA
Adapter 1.5 A, IINLIM (REG00[5:0]) = 1500 mA130014001500mA
IIN(START)Input current regulation during system start upVSYS = 2.2 V, IINLIM (REG00[5:0])> = 200 mA200mA
KILIMIINMAX = KILIM/RILIMInput current regulation by ILIM pin = 1.5 A320355390A x Ω
D+/D- DETECTION
V(0P6_VSRC)D+/D– voltage source (0.6 V)0.50.60.7V
V(3p45_VSRC)D+/D– voltage source (3.45 V)3.33.453.6V
I(10UA_ISRC)D+ connection check current source71014µA
I(100UA_ISINK)D+/D– current sink (100 µA)50100150µA
I(DPDM_LKG)D+/D– Leakage currentD–, switch open–11µA
D+, switch open–11µA
I(1P6MA_ISINK)D+/D– current sink (1.6 mA)1.451.601.75µA
V(0P4_VTH)D+/D– low comparator threshold250400mV
V(0P8_VTH)D+ low comparator threshold0.8V
V(2P7_VTH)D+/D– comparator threshold for non-standard adapter detection (divider 1, 3, or 4)2.552.85V
V(2P0_VTH)D+/D– comparator threshold for non-standard adapter detection (divider 1, 3)1.852.15V
V(1P2_VTH)D+/D– comparator threshold for non-standard adapter detection (divider 2)1.051.35V
R(D–_DWN)D– pulldown for connection check14.2524.8kΩ
BAT OVERVOLTAGE/CURRENT PROTECTION
VBAT(OVP)Battery over-voltage thresholdVBAT rising, as percentage of VBAT(REG)104%
VBAT(OVP_HYST)Battery over-voltage hysteresisVBAT falling, as percentage of VBAT(REG)2%
IBAT(FET_OCP)System over-current threshold9A
THERMAL REGULATION AND THERMAL SHUTDOWN
TREGJunction temperature regulation accuracyREG08[1:0] = 11120°C
TSHUTThermal shutdown rising temperatureTemperature rising160°C
TSHUT(HYS)Thermal shutdown hysteresisTemperature falling30°C
V(LTF)Cold temperature threshold, TS pin voltage rising thresholdAs percentage to V(REGN)72.75%73.25%73.75%
V(LTF_HYS)Cold temperature hysteresis, TS pin voltage fallingAs percentage to V(REGN)0.4%
V(HTF)Hot temperature TS pin voltage rising thresholdAs percentage to V(REGN)47.75%48.25%48.75%
V(TCO)Cut-off temperature TS pin voltage falling thresholdAs percentage to V(REGN)44.25%44.75%45.25%
COLD/HOT THERMISTOR COMPARATOR (BOOST MODE)
V(BCOLD1)Cold temperature threshold 1, TS pin voltage rising thresholdAs percentage to VREGN REG01[5] = 1
(Approximately –20°C w/ 103AT)		79.5%80%80.5%
V(BCOLD1_HYS)Cold temperature threshold 1, TS pin voltage falling thresholdAs percentage to VREGN REG01[5] = 11%
V(BHOT2)Hot temperature threshold 2, TS pin voltage falling thresholdAs percentage to VREGN REG01[7:6] = 10
(Approx. 65°C w/ 103AT)		30.75%31.25%31.75%
V(BHOT2_HYS)Hot temperature threshold 2, TS pin voltage rising thresholdAs percentage to VREGN REG01[7:6] =103%
PWM
FSWPWM switching frequency, and digital clockOscillator frequency1.321.68MHz
DMAXMaximum PWM duty cycle97%
BOOST MODE OPERATION
V(OTG_REG_RANGE)Typical boost mode regulation voltage range4.555.55V
V(OTG_REG_STEP)Typical boost mode regulation voltage step64mV
V(OTG_REG_ACC)Boost mode regulation voltage accuracyI(PMID) = 0 A, BOOSTV=5.126V (REG0A[7:4] = 1001)–3%3%
V(OTG_BAT)Battery voltage exiting boost modeBAT falling2.62.9V
I(OTG)Boost mode output current range 3.1A
V(OTG_OVP)Boost mode over-voltage thresholdRising threshold5.86V
REGN LDO
V(REGN)REGN LDO output voltage V(VBUS) = 9 V, I(REGN) = 40 mA5.666.4V
V(VBUS) = 5 V, I(REGN) = 20 mA4.74.8V
I(REGN)REGN LDO current limit V(VBUS) = 9 V, V(REGN) = 3.8 V50mA
ANALOG-TO-DIGITAL CONVERTER (ADC)
RESResolutionRising threshold7bits
VBAT(RANGE)Typical battery voltage rangeV(VBUS) > VBAT + V(SLEEP) or OTG mode is enabled2.3044.848V
V(VBUS) < VBAT + V(SLEEP) and OTG mode is disabledVSYS_MIN4.848V
V(BAT_RES)Typical battery voltage resolution20mV
V(SYS_RANGE)Typical system voltage rangeV(VBUS) > VBAT + V(SLEEP) or OTG mode is enabled2.3044.848V
V(VBUS) < VBAT + V(SLEEP) and OTG mode is disabledVSYS_MIN4.848V
V(SYS_RES)Typical system voltage resolution20mV
V(VBUS_RANGE)Typical VVBUS voltage rangeV(VBUS) > VBAT + V(SLEEP) or OTG mode is enabled2.615.3V
V(VBUS_RES)Typical VVBUS voltage resolution100mV
IBAT(RANGE)Typical battery charge current rangeV(VBUS) > VBAT + V(SLEEP) and VBAT > VBAT(SHORT)06.4A
IBAT(RES)Typical battery charge current resolution50mA
V(TS_RANGE)Typical TS voltage range21%80%
V(TS_RES)Typical TS voltage resolution0.47%
LOGIC I/O PIN (OTG, CE, PSEL,QON)
VIHInput high threshold level1.3
VILInput low threshold level0.4V
IIN(BIAS)High Level Leakage CurrentPull-up rail 1.8 V1µA
V(QON)Internal /QON pull-upBattery only modeBATV
V(VBUS) = 9 V5.8V
V(VBUS) = 5 V4.3V
R(QON)Internal /QON pull-up resistance200kΩ
LOGIC I/O PIN (INT, STAT, PG, DSEL)
VOLOutput low threshold levelSink current = 5 mA, sink current0.4V
IOUT_BIASHigh level leakage currentPull-up rail 1.8 V1µA
I2C INTERFACE (SCL, SDA)
VIHInput high threshold level, SCL and SDAPull-up rail 1.8 V1.3
VILInput low threshold levelPull-up rail 1.8 V0.4V
VOLOutput low threshold levelSink current = 5 mA, sink current0.4V
IBIASHigh level leakage currentPull-up rail 1.8 V1µA