SLUSC88C March   2015  – October 2022 BQ25895

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  Device Power-On-Reset (POR)
      2. 8.2.2  Device Power Up from Battery without Input Source
      3. 8.2.3  Device Power Up from Input Source
        1. 8.2.3.1 Power Up REGN Regulation (LDO)
        2. 8.2.3.2 Poor Source Qualification
        3. 8.2.3.3 Input Source Type Detection
          1. 8.2.3.3.1 D+/D– Detection Sets Input Current Limit
          2. 8.2.3.3.2 Force Input Current Limit Detection
        4. 8.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.2.3.5 Converter Power-Up
      4. 8.2.4  Input Current Optimizer (ICO)
      5. 8.2.5  Boost Mode Operation from Battery
      6. 8.2.6  Power Path Management
        1. 8.2.6.1 Narrow VDC Architecture
        2. 8.2.6.2 Dynamic Power Management
        3. 8.2.6.3 Supplement Mode
      7. 8.2.7  Battery Charging Management
        1. 8.2.7.1 Autonomous Charging Cycle
        2. 8.2.7.2 Battery Charging Profile
        3. 8.2.7.3 Charging Termination
        4. 8.2.7.4 Resistance Compensation (IRCOMP)
        5. 8.2.7.5 Thermistor Qualification
          1. 8.2.7.5.1 Cold/Hot Temperature Window in Charge Mode
          2. 8.2.7.5.2 Cold/Hot Temperature Window in Boost Mode
        6. 8.2.7.6 Charging Safety Timer
      8. 8.2.8  Battery Monitor
      9. 8.2.9  Status Outputs (STAT, and INT)
        1. 8.2.9.1 Charging Status Indicator (STAT)
        2. 8.2.9.2 Interrupt to Host (INT)
      10. 8.2.10 BATET (Q4) Control
        1. 8.2.10.1 BATFET Disable Mode (Shipping Mode)
        2. 8.2.10.2 BATFET Enable (Exit Shipping Mode)
        3. 8.2.10.3 BATFET Full System Reset
      11. 8.2.11 Current Pulse Control Protocol
      12. 8.2.12 Input Current Limit on ILIM
      13. 8.2.13 Thermal Regulation and Thermal Shutdown
        1. 8.2.13.1 Thermal Protection in Buck Mode
        2. 8.2.13.2 Thermal Protection in Boost Mode
      14. 8.2.14 Voltage and Current Monitoring in Buck and Boost Mode
        1. 8.2.14.1 Voltage and Current Monitoring in Buck Mode
          1. 8.2.14.1.1 Input Overvoltage (ACOV)
          2. 8.2.14.1.2 System Overvoltage Protection (SYSOVP)
        2. 8.2.14.2 Current Monitoring in Boost Mode
          1. 8.2.14.2.1 Boost Mode Overvoltage Protection
      15. 8.2.15 Battery Protection
        1. 8.2.15.1 Battery Overvoltage Protection (BATOVP)
        2. 8.2.15.2 Battery Over-Discharge Protection
        3. 8.2.15.3 System Overcurrent Protection
      16. 8.2.16 Serial Interface
        1. 8.2.16.1 Data Validity
        2. 8.2.16.2 START and STOP Conditions
        3. 8.2.16.3 Byte Format
        4. 8.2.16.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.2.16.5 Target Address and Data Direction Bit
        6. 8.2.16.6 Single Read and Write
        7. 8.2.16.7 Multi-Read and Multi-Write
    3. 8.3 Device Functional Modes
      1. 8.3.1 Host Mode and Default Mode
    4. 8.4 Register Maps
      1. 8.4.1  REG00
      2. 8.4.2  REG01
      3. 8.4.3  REG02
      4. 8.4.4  REG03
      5. 8.4.5  REG04
      6. 8.4.6  REG05
      7. 8.4.7  REG06
      8. 8.4.8  REG07
      9. 8.4.9  REG08
      10. 8.4.10 REG09
      11. 8.4.11 REG0A
      12. 8.4.12 REG0B
      13. 8.4.13 REG0C
      14. 8.4.14 REG0D
      15. 8.4.15 REG0E
      16. 8.4.16 REG0F
      17. 8.4.17 REG10
      18. 8.4.18 REG11
      19. 8.4.19 REG12
      20. 8.4.20 REG13
      21. 8.4.21 REG14
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Buck Input Capacitor
        3. 9.2.2.3 System Output Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Glossary
    6. 12.6 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.3.3 Input Source Type Detection

After the VBUS_GD bit is set and REGN LDO is powered, the charger device runs Section 8.2.3.3 when AUTO_DPDM_EN bit is set.

The BQ25895 follows the USB Battery Charging Specification 1.2 (BC1.2) and to detect input source (SDP/CDP/DCP) and non-standard adapter through USB D+/D- lines. In addition, when USB DCP is detected, it initiates adjustable high voltage adapter handshake on D+/D-. The device supports MaxCharge™ handshake when MAXC_EN or HVDCP_EN is set.

After input source type detection, an INT pulse is asserted to the host. In addition, the following registers and pin are changed:

  1. Input Current Limit (IINLIM) register is changed to set current limit
  2. PG_STAT bit is set
  3. SDP_STAT bit is updated to indicate USB100 or other input source

The host can over-write IINLIM register to change the input current limit if needed. The charger input current is always limited by the lower of IINLIM register or ILIM pin at all-time regardless of Input Current Optimizer (ICO) is enable or disabled.

When AUTO_DPDM_EN is disabled, the Section 8.2.3.3 is bypassed. The Input Current Limit (IINLIM) register, VBUS_STAT, and SPD_STAT bits are unchanged from previous values.