SLUSC76C July   2015  – May 2018

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1  Device Power-On-Reset (POR)
      2. 9.2.2  Device Power Up from Battery without Input Source
      3. 9.2.3  Device Power Up from Input Source
        1. 9.2.3.1 Power Up REGN Regulation (LDO)
        2. 9.2.3.2 Poor Source Qualification
        3. 9.2.3.3 Input Source Type Detection
          1. 9.2.3.3.1 PSEL Pins Set Input Current Limit
          2. 9.2.3.3.2 Force Input Current Limit Detection
        4. 9.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.2.3.5 Converter Power-Up
      4. 9.2.4  Input Current Optimizer (ICO)
      5. 9.2.5  Boost Mode Operation from Battery
      6. 9.2.6  Power Path Management
        1. 9.2.6.1 Narrow VDC Architecture
        2. 9.2.6.2 Dynamic Power Management
        3. 9.2.6.3 Supplement Mode
      7. 9.2.7  Battery Charging Management
        1. 9.2.7.1 Autonomous Charging Cycle
        2. 9.2.7.2 Battery Charging Profile
        3. 9.2.7.3 Charging Termination
        4. 9.2.7.4 Resistance Compensation (IRCOMP)
        5. 9.2.7.5 Thermistor Qualification
          1. 9.2.7.5.1 JEITA Guideline Compliance in Charge Mode
          2. 9.2.7.5.2 Cold/Hot Temperature Window in Boost Mode
        6. 9.2.7.6 Charging Safety Timer
      8. 9.2.8  Battery Monitor
      9. 9.2.9  Status Outputs (PG, STAT, and INT)
        1. 9.2.9.1 Power Good Indicator (PG)
        2. 9.2.9.2 Charging Status Indicator (STAT)
        3. 9.2.9.3 Interrupt to Host (INT)
      10. 9.2.10 BATET (Q4) Control
        1. 9.2.10.1 BATFET Disable Mode (Shipping Mode)
        2. 9.2.10.2 BATFET Enable (Exit Shipping Mode)
        3. 9.2.10.3 BATFET Full System Reset
      11. 9.2.11 Current Pulse Control Protocol
      12. 9.2.12 Input Current Limit on ILIM
      13. 9.2.13 Thermal Regulation and Thermal Shutdown
        1. 9.2.13.1 Thermal Protection in Buck Mode
        2. 9.2.13.2 Thermal Protection in Boost Mode
      14. 9.2.14 Voltage and Current Monitoring in Buck and Boost Mode
        1. 9.2.14.1 Voltage and Current Monitoring in Buck Mode
          1. 9.2.14.1.1 Input Overvoltage (ACOV)
          2. 9.2.14.1.2 System Overvoltage Protection (SYSOVP)
        2. 9.2.14.2 Current Monitoring in Boost Mode
          1. 9.2.14.2.1 VBUS Overcurrent Protection
          2. 9.2.14.2.2 Boost Mode Overvoltage Protection
      15. 9.2.15 Battery Protection
        1. 9.2.15.1 Battery Overvoltage Protection (BATOVP)
        2. 9.2.15.2 Battery Over-Discharge Protection
        3. 9.2.15.3 System Overcurrent Protection
      16. 9.2.16 Serial Interface
        1. 9.2.16.1 Data Validity
        2. 9.2.16.2 START and STOP Conditions
        3. 9.2.16.3 Byte Format
        4. 9.2.16.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.2.16.5 Slave Address and Data Direction Bit
        6. 9.2.16.6 Single Read and Write
        7. 9.2.16.7 Multi-Read and Multi-Write
    3. 9.3 Device Functional Modes
      1. 9.3.1 Host Mode and Default Mode
    4. 9.4 Register Maps
      1. 9.4.1  REG00
        1. Table 6. REG00
      2. 9.4.2  REG01
        1. Table 7. REG01
      3. 9.4.3  REG02
        1. Table 8. REG02
      4. 9.4.4  REG03
        1. Table 9. REG03
      5. 9.4.5  REG04
        1. Table 10. REG04
      6. 9.4.6  REG05
        1. Table 11. REG05
      7. 9.4.7  REG06
        1. Table 12. REG06
      8. 9.4.8  REG07
        1. Table 13. REG07
      9. 9.4.9  REG08
        1. Table 14. REG08
      10. 9.4.10 REG09
        1. Table 15. REG09
      11. 9.4.11 REG0A
        1. Table 16. REG0A
      12. 9.4.12 REG0B
        1. Table 17. REG0B
      13. 9.4.13 REG0C
        1. Table 18. REG0C
      14. 9.4.14 REG0D
        1. Table 19. REG0D
      15. 9.4.15 REG0E
        1. Table 20. REG0E
      16. 9.4.16 REG0F
        1. Table 21. REG0F
      17. 9.4.17 REG10
        1. Table 22. REG10
      18. 9.4.18 REG11
        1. Table 23. REG11
      19. 9.4.19 REG12
        1. Table 24. REG12
      20. 9.4.20 REG13
        1. Table 25. REG13
      21. 9.4.21 REG14
        1. Table 26. REG14
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Buck Input Capacitor
        3. 10.2.2.3 System Output Capacitor
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Electrical Characteristics

VVBUS_UVLOZ< VVBUS< VACOV and VVBUS> VBAT + VSLEEP, TJ = –40°C to +125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
IBAT Battery discharge current (BAT, SW, SYS) in buck mode VBAT = 4.2 V, V(VBUS)< V(UVLO), leakage between BAT and VBUS 5 µA
High-Z mode, no VBUS, BATFET disabled (REG09[5]=1), battery monitor disabled, TJ< 85°C 12 23 µA
High-Z mode, no VBUS, BATFET enabled (REG09[5]=0), battery monitor disabled, TJ< 85°C 32 60 µA
I(VBUS_HIZ) Input supply current (VBUS) in buck mode when High-Z mode is enabled V(VBUS)= 5 V, High-Z mode, no battery, battery monitor disabled 15 35 µA
V(VBUS)= 12 V, High-Z mode, no battery, battery monitor disabled 25 50 µA
I(VBUS) Input supply current (VBUS) in buck mode VBUS> V(UVLO), VBUS> VBAT, converter not switching 1.5 3 mA
VBUS> V(UVLO), VBUS> VBAT, converter switching, VBAT = 3.2 V, ISYS = 0A 3 mA
VBUS> V(UVLO), VBUS> VBAT, converter switching, VBAT = 3.8 V, ISYS = 0 A 3 mA
I(BOOST) Battery discharge current in boost mode VBAT = 4.2 V, boost mode, I(VBUS)= 0 A, converter switching 5 mA
VBUS/BAT POWER UP
V(VBUS_OP) VBUS operating range 3.9 14 V
V(VBUS_UVLOZ) VBUS for active I2C, no battery 3.6 V
V(SLEEP) Sleep mode falling threshold 25 65 120 mV
V(SLEEPZ) Sleep mode rising threshold 130 250 370 mV
V(ACOV) VBUS over-voltage rising threshold 14 14.6 V
VBUS over-voltage falling threshold 13.5 14 V
VBAT(UVLOZ) Battery for active I2C, no VBUS 2.3 V
VBAT(DPL) Battery depletion falling threshold 2.15 2.5 V
VBAT(DPLZ) Battery depletion rising threshold 2.35 2.7 V
V(VBUSMIN) Bad adapter detection threshold 3.8 V
I(BADSRC) Bad adapter detection current source 30 mA
POWER-PATH MANAGEMENT
VSYS Typical system regulation voltage I(SYS) = 0 A, VBAT> VSYS(MIN), BATFET Disabled (REG09[5]=1) VBAT+
50 mV		 V
I(SYS) = 0 A, VBAT< VSYS(MIN), BATFET Disabled (REG09[5]=1) VSYS(MIN) +
150 mV		 V
VSYS(MIN) Minimum DC system voltage output VBAT< VSYS(MIN), SYS_MIN = 3.5 V (REG03[3:1]=101), ISYS= 0 A 3.50 3.65 V
VSYS(MAX) Maximum DC system voltage output VBAT = 4.35 V, SYS_MIN = 3.5V (REG03[3:1]=101), ISYS= 0 A 4.40 4.42 V
RON(RBFET) Top reverse blocking MOSFET(RBFET) on-resistance between VBUS and PMID TJ = –40°C to +85°C 27 38 mΩ
TJ= –40°C to +125°C 27 44 mΩ
RON(HSFET) Top switching MOSFET (HSFET) on-resistance between PMID and SW TJ = –40°C to +85°C 33 45 mΩ
TJ = –40°C to +125°C 33 53 mΩ
RON(LSFET) Bottom switching MOSFET (LSFET) on-resistance between SW and GND TJ = –40°C to +85°C 18 26 mΩ
TJ = –40°C to +125°C 18 30 mΩ
V(FWD) BATFET forward voltage in supplement mode BAT discharge current 10 mA 30 mV
VBAT(GD) Battery good comparator rising threshold VBAT rising 3.4 3.55 3.7 V
VBAT(GD_HYST) Battery good comparator falling threshold VBAT falling 100 mV
BATTERY CHARGER
VBAT(REG_RANGE) Typical charge voltage range 3.840 4.608 V
VBAT(REG_STEP) Typical charge voltage step 16 mV
VBAT(REG) Charge voltage resolution accuracy VBAT = 4.208 V (REG06[7:2]=010111) or
VBAT = 4.352 V (REG06[7:2]=100000)
TJ = –40°C to +85°C		 -0.5% 0.5%
I(CHG_REG_RANGE) Typical fast charge current regulation range 0 3008 mA
I(CHG_REG_STEP) Typical fast charge current regulation step 64 mA
I(CHG_REG_ACC) Fast charge current regulation accuracy VBAT = 3.1 V or 3.8 V, ICHG = 128 mA
TJ = –40°C to +85°C		 -20% 20%
VBAT= 3.1 V or 3.8 V, ICHG = 256 mA
TJ = –40°C to +85°C		 -10% 10%
VBAT= 3.1 V or 3.8 V, ICHG=1792 mA
TJ = –40°C to +85°C		 -5% 5%
VBAT(LOWV) Battery LOWV falling threshold Fast charge to precharge, BATLOWV (REG06[1]) = 1 2.6 2.8 2.9 V
Battery LOWV rising threshold Precharge to fast charge, BATLOWV (REG06[1])=1
(Typical 200-mV hysteresis)		 2.8 3 3.1 V
I(PRECHG_RANGE) Precharge current range 64 1024 mA
I(PRECHG_STEP) Typical precharge current step 64 mA
I(PRECHG_ACC) Precharge current accuracy VBAT=2.6 V, IPRECHG = 256 mA –10% +10%
I(TERM_RANGE) Termination current range 64 1024 mA
I(TERM_STEP) Typical termination current step 64 mA
I(TERM_ACC) Termination current accuracy ITERM = 256 mA, ICHG<= 1344 mA
TJ = –20°C to +85°C		 –12% 12%
ITERM = 256 mA, ICHG> 1344 mA
TJ = –20°C to +85°C		 –20% 20%
V(SHORT) Battery short voltage VBAT falling 2 V
V(SHORT_HYST) Battery short voltage hysteresis VBAT rising 200 mV
I(SHORT) Battery short current VBAT < 2.2 V 100 mA
V(RECHG) Recharge threshold below VBATREG VBAT falling, VRECHG (REG06[0]=0) = 0 100 mV
VBAT falling, VRECHG (REG06[0]=0) = 1 200 mV
IBAT(LOAD) Battery discharge load current VBAT = 4.2 V 15 mA
ISYS(LOAD) System discharge load current VSYS = 4.2 V 30 mA
RON(BATFET) SYS-BAT MOSFET (BATFET) on-resistance TJ = 25°C 11 13 mΩ
TJ = –40°C to +125°C 11 19 mΩ
INPUT VOLTAGE / CURRENT REGULATION
VIN(DPM_RANGE) Typical Input voltage regulation range 3.9 15.3 V
VIN(DPM_STEP) Typical Input voltage regulation step 100 mV
VIN(DPM_ACC) Input voltage regulation accuracy VINDPM = 4.4 V, 9 V 3% 3%
IIN(DPM_RANGE) Typical Input current regulation range 100 3250 mA
IIN(DPM_STEP) Typical Input current regulation step 50 mA
IIN(DPM100_ACC) Input current 100-mA regulation accuracy
VBAT = 5 V, current pulled from SW		 IINLIM (REG00[5:0]) =100 mA 85 90 100 mA
IIN(DPM_ACC) Input current regulation accuracy
VBAT = 5 V, current pulled from SW		 USB150, IINLIM (REG00[5:0]) = 150 mA 125 135 150 mA
USB500, IINLIM (REG00[5:0]) = 500 mA 440 470 500 mA
USB900, IINLIM (REG00[5:0]) = 900 mA 750 825 900 mA
Adapter 1.5 A, IINLIM (REG00[5:0]) = 1500 mA 1300 1400 1500 mA
IIN(START) Input current regulation during system start up VSYS = 2.2 V, IINLIM (REG00[5:0])> = 200 mA 200 mA
KILIM IINMAX = KILIM/RILIM Input current regulation by ILIM pin = 1.5 A 320 355 390 A x Ω
KILIM IINMAX = KILIM/RILIM Input current regulation by ILIM pin = 1.5 A 320 355 390 A x Ω
BAT OVER-VOLTAGE/CURRENT PROTECTION
VBAT(OVP) Battery over-voltage threshold VBAT rising, as percentage of VBAT(REG) 104%
VBAT(OVP_HYST) Battery over-voltage hysteresis VBAT falling, as percentage of VBAT(REG) 2%
IBAT(FET_OCP) System over-current threshold 9 A
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG Junction temperature regulation accuracy REG08[1:0] = 11 120 °C
TSHUT Thermal shutdown rising temperature Temperature rising 160 °C
TSHUT(HYS) Thermal shutdown hysteresis Temperature falling 30 °C
JEITA THERMISTOR COMPARATOR (BUCK MODE)
V(T1) T1 (0°C) threshold, charge suspended T1 below this temperature. As percentage to V(REGN) 72.75% 73.25% 73.75%
V(T1_HYS) Charge back to ICHG/2 (REG04[6:0]) and VREG (REG06[7:2]) above this temperature. As percentage to V(REGN) 1.4%
V(T2) T2 (10°C) threshold, charge back to ICHG/2 (REG04[6:0]) and VREG (REG06[7:2]) below this temperature. As percentage to V(REGN) 67.75% 68.25% 68.75%
V(T2_HYS) Charge back to ICHG (REG04[6:0]) and VREG (REG06[7:2]) above this temperature. As percentage to V(REGN) 1.4%
V(T3) T3 (45°C) threshold, charge back to ICHG (REG04[6:0]) and VREG-200 mV (REG06[7:2]) above this temperature. As percentage to V(REGN) 44.25v 44.75% 45.25%
V(T3_HYS) Charge back to ICHG (REG04[6:0]) and VREG (REG06[7:2]) below this temperature. As percentage to V(REGN) 1%
V(T5) T5 (60°C) threshold, charge suspended above this temperature. As percentage to V(REGN) 33.875% 34.375% 34.875%
V(T5_HYS) Charge back to ICHG (REG04[6:0]) and VREG-200 mV (REG06[7:2]) below this temperature. As percentage to V(REGN) 1.25%
COLD/HOT THERMISTOR COMPARATOR (BOOST MODE)
V(BCOLD0) Cold temperature threshold, TS pin voltage rising threshold As percentage to VREGN , REG01[5] = 0
(Approx. -10°C w/ 103AT) 		76.5% 77% 77.5%
V(BCOLD0_HYS) Cold temperature threshold, TS pin voltage falling threshold As percentage to VREGN REG01[5] = 0 1%
V(BCOLD1) Cold temperature threshold 1, TS pin voltage rising threshold As percentage to VREGN REG01[5] = 1
(Approximately –20°C w/ 103AT) 		79.5% 80% 80.5%
V(BCOLD1_HYS) Cold temperature threshold 1, TS pin voltage falling threshold As percentage to VREGN REG01[5] = 1 1%
V(BHOT0) Hot temperature threshold, TS pin voltage falling threshold As percentage to VREGN REG01[7:6] = 01
(Approx. 55°C w/ 103AT) 		37.25% 37.75% 38.25%
V(BHOT0_HYS) Hot temperature threshold, TS pin voltage rising threshold As percentage to VREGN REG01[7:6] = 01 3%
V(BHOT1) Hot temperature threshold 1, TS pin voltage falling threshold As percentage to VREGN REG01[7:6] = 00
(Approx. 60°C w/ 103AT) 		33.875% 34.375% 34.875%
V(BHOT1_HYS) Hot temperature threshold 1, TS pin voltage rising threshold As percentage to VREGN REG01[7:6] = 00 3%
V(BHOT2) Hot temperature threshold 2, TS pin voltage falling threshold As percentage to VREGN REG01[7:6] = 10
(Approx. 65°C w/ 103AT) 		30.75% 31.25% 31.75%
V(BHOT2_HYS) Hot temperature threshold 2, TS pin voltage rising threshold As percentage to VREGN REG01[7:6] =10 3%
PWM
FSW PWM switching frequency, and digital clock Oscillator frequency 1.32 1.68 MHz
DMAX Maximum PWM duty cycle 97%
BOOST MODE OPERATION
V(OTG_REG_RANGE) Typical boost mode regulation voltage range 4.55 5.55 V
V(OTG_REG_STEP) Typical boost mode regulation voltage step 64 mV
V(OTG_REG_ACC) Boost mode regulation voltage accuracy I(VBUS) = 0 A, BOOSTV=4.998V (REG0A[7:4] = 0111) –3% 3%
V(OTG_BAT1) Minimum battery voltage to exit boost mode BAT falling, MIN_VBAT_SEL=0 2.7 2.9 V
V(OTG_BAT2) Minimum battery voltage to exit boost mode BAT falling, MIN_VBAT_SEL=1 2.4 2.6 V
V(OTG_BAT_EN) Minimum battery voltage to enter boost mode BAT rising, MIN_VBAT_SEL=0 2.9 3.1 V
BAT rising, MIN_VBAT_SEL=1 2.7 2.9 V
I(OTG) Typical boost mode output current range 0.5 2 A
I(OTG_OCP_ACC) Boost mode RBFET over-current protection accuracy BOOST_LIM =1.2 A (REG0A[2:0]=010) 1.2 1.65 A
V(OTG_OVP) Boost mode over-voltage threshold Rising threshold 5.8 6 V
REGN LDO
V(REGN) REGN LDO output voltage V(VBUS) = 9 V, I(REGN) = 40 mA 4.8 5 5.5 V
V(VBUS) = 5 V, I(REGN) = 20 mA 4.7 4.8 V
I(REGN) REGN LDO current limit V(VBUS) = 9 V, V(REGN) = 3.8 V 50 mA
ANALOG-TO-DIGITAL CONVERTER (ADC)
RES Resolution Rising threshold 7 bits
VBAT(RANGE) Typical battery voltage range V(VBUS)> VBAT + V(SLEEP) or OTG mode is enabled 2.304 4.848 V
V(VBUS)< VBAT + V(SLEEP) and OTG mode is disabled VSYS_MIN 4.848 V
V(BAT_RES) Typical battery voltage resolution 20 mV
V(SYS_RANGE) Typical system voltage range V(VBUS)> VBAT + V(SLEEP) or OTG mode is enabled 2.304 4.848 V
V(VBUS)< VBAT + V(SLEEP) and OTG mode is disabled VSYS_MIN 4.848 V
V(SYS_RES) Typical system voltage resolution 20 mV
V(VBUS_RANGE) Typical VVBUS voltage range V(VBUS)> VBAT + V(SLEEP) or OTG mode is enabled 2.6 15.3 V
V(VBUS_RES) Typical VVBUS voltage resolution 100 mV
IBAT(RANGE) Typical battery charge current range V(VBUS)> VBAT + V(SLEEP) and VBAT> VBAT(SHORT) 0 6.4 A
IBAT(RES) Typical battery charge current resolution 50 mA
V(TS_RANGE) Typical TS voltage range 21% 80%
V(TS_RES) Typical TS voltage resolution 0.47%
LOGIC I/O PIN (OTG, CE, PSEL, QON)
VIH Input high threshold level 1.3
VIL Input low threshold level 0.4 V
IIN(BIAS) High Level Leakage Current Pull-up rail 1.8 V 1 µA
V(QON) Internal /QON pull-up Battery only mode BAT V
V(VBUS) = 9 V 5.8 V
V(VBUS) = 5 V 4.3 V
R(QON) Internal /QON pull-up resistance 200 kΩ
LOGIC I/O PIN (INT, STAT, PG)
VOL Output low threshold level Sink current = 5 mA, sink current 0.4 V
IOUT_BIAS High level leakage current Pull-up rail 1.8 V 1 µA
I2C INTERFACE (SCL, SDA)
VIH Input high threshold level, SCL and SDA Pull-up rail 1.8 V 1.3
VIL Input low threshold level Pull-up rail 1.8 V 0.4 V
VOL Output low threshold level Sink current = 5 mA, sink current 0.4 V
IBIAS High level leakage current Pull-up rail 1.8 V 1 µA