The Texas Instruments single-cell bq27320 battery fuel gauge requires very minimal configuration and system microcontroller firmware development, leading to quick system bring-up. The bq27320 uses the Compensated End-of-Discharge Voltage (CEDV) gas gauging algorithm for fuel gauging, and provides information such as remaining battery capacity (mAh), state-of-charge (%), runtime-to-empty (min), battery voltage (mV), temperature (°C) and state-of-health (%).
TI customers can tune chemistry parameters using TI's web-based tool, GAUGEPARCAL.
Configurable interrupts help save system power and free up the host from continuous polling. Accurate temperature sensing is supported via an external thermistor.
Battery fuel gauging with the bq27320 requires only PACK+ (P+), PACK– (P–), and optional thermistor (T) connections to a removable battery pack or embedded battery circuit. The device uses a 15-ball NanoFree™ (DSBGA) package. It is ideal for space-constrained applications.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
bq27320 | YZF (15) | 1.375 mm x 2.75 mm x 1.75 mm |
DATE | REVISION | NOTES |
---|---|---|
March 2016 | A | PRODUCT PREVIEW to Production Data |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
SRP | A1 | IA(1) | Analog input pin connected to the internal coulomb counter with a Kelvin connection where SRP is nearest the PACK– connection. Connect to 5-mΩ to 20-mΩ sense resistor. |
SRN | B1 | IA | Analog input pin connected to the internal coulomb counter with a Kelvin connection where SRN is nearest the Vss connection. Connect to 5-mΩ to 20-mΩ sense resistor. |
VSS | C1, C2 | P | Device ground |
VCC | D1 | P | Regulator output and bq27320 processor power. Decouple with 1-μF ceramic capacitor to Vss. |
REGIN | E1 | P | Regulator input. Decouple with 0.1-μF ceramic capacitor to VSS. |
SOC_INT | A2 | O | SOC state interrupts output. Generates a pulse under the conditions specified by (1). Open drain output |
BAT_GD | B2 | O | Battery Good push-pull indicator output. Active-low and output disabled by default. Polarity is configured via Op Config [BATG_POL] and the output is enabled via OpConfig C [BATGSPUEN]. |
CE | D2 | I | Chip Enable. Internal LDO is disconnected from REGIN when driven low. Note: CE has an internal ESD protection diode connected to REGIN. Recommend maintaining VCE ≤ VREGIN under all conditions. |
BAT | E2 | I | Cell-voltage measurement input. ADC input. Recommend 4.8V maximum for conversion accuracy. |
SCL | A3 | I | Slave I2C serial communications clock input line for communication with system (Master). Open-drain I/O. Use with 10-kΩ pull-up resistor (typical). |
SDA | B3 | I/O | Slave I2C serial communications data line for communication with system (Master). Open-drain I/O. Use with 10-kΩ pull-up resistor (typical). |
SDQ | C3 | O | Communication interface to Authentication ID IC, using the SDQ protocol |
TS | D3 | IA | Pack thermistor voltage sense (use 103AT-type thermistor). ADC input |
BI/TOUT | E3 | I/O | Battery-insertion detection input. Power pin for pack thermistor network. Thermistor-multiplexer control pin. Use with pull-up resistor >1MΩ (1.8 MΩ typical). |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VREGIN | Regulator input range | –0.3 | 5.5 | V |
–0.3 | 6.0 (2) | V | ||
VCE | CE input pin | –0.3 | VREGIN + 0.3 | V |
VCC | Supply voltage range | –0.3 | 2.75 | V |
VIOD | Open-drain I/O pins (SDA, SCL, SOC_INT) | –0.3 | 5.5 | V |
VBAT | BAT input pin | –0.3 | 5.5 | V |
–0.3 | 6.0 (2) | V | ||
VI | Input voltage range to all other pins (BI/TOUT, TS, SRP, SRN, SDQ, BAT_GD) |
–0.3 | VCC + 0.3 | V |
TA | Operating free-air temperature range | –40 | 85 | °C |
TFUNC | Functional Temperature | –40 | 110 | °C |
TSTG | Storage temperature range | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic Discharge | Human body model (HBM) ESD stress voltage(1), BAT pin | 1500 | V |
Human-body model (HBM), all other pins | 2000 | |||
Charged-device model (CDM) ESD stress voltage(1) | 500 | V |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VREGIN | Supply voltage | No operating restrictions | 2.8 | 4.5 | V | |
No FLASH writes | 2.45 | 2.8 | ||||
CREGIN | External input capacitor for internal LDO between REGIN and VSS | Nominal capacitor values specified. Recommend a 5% ceramic X5R type capacitor located close to the device. | 0.1 | μF | ||
CLDO25 | External output capacitor for internal LDO between VCC and VSS | 0.47 | 1 | μF | ||
tPUCD | Power-up communication delay | 250 | ms |
THERMAL METRIC(1) | bq27320 | UNIT | |
---|---|---|---|
YZF (DSBGA) | |||
15 PINS |
|||
RθJA | Junction-to-ambient thermal resistance | 70 | °C/W |
RθJCtop | Junction-to-case (top) thermal resistance | 17 | °C/W |
RθJB | Junction-to-board thermal resistance | 20 | °C/W |
ψJT | Junction-to-top characterization parameter | 1 | °C/W |
ψJB | Junction-to-board characterization parameter | 18 | °C/W |
RθJCbot | Junction-to-case (bottom) thermal resistance | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ICC(1) | Normal operating-mode current | Fuel gauge in NORMAL mode ILOAD > Sleep Current |
118 | μA | ||
ISNOOZE(1) | Sleep+ operating mode current | Fuel gauge in SNOOZE mode ILOAD < Sleep Current |
62 | μA | ||
ISLP(1) | Low-power storage-mode current | Fuel gauge in SLEEP mode ILOAD < Sleep Current |
23 | μA | ||
IHIB(1) | Hibernate operating-mode current | Fuel gauge in HIBERNATE mode ILOAD < Hibernate Current |
8 | μA | ||
ISHD(1) | SHUTDOWN mode current | Fuel gauge in SHUTDOWN mode CE Pin < VIL(CE) max. |
1 | μA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VOL | Output voltage, low (SCL, SDA, SOC_INT, SDQ, BAT_GD) | IOL = 3 mA | 0.4 | V | ||
VOH(PP) | Output voltage, high (SDQ, BAT_GD) | IOH = –1 mA | VCC – 0.5 | V | ||
VOH(OD) | Output voltage, high (SDA, SCL, SOC_INT) | External pullup resistor connected to VCC | VCC – 0.5 | |||
VIL | Input voltage, low (SDA, SCL) | –0.3 | 0.6 | V | ||
Input voltage, low (BI/TOUT) | BAT INSERT CHECK mode active | –0.3 | 0.6 | |||
VIH | Input voltage, high (SDA, SCL) | 1.2 | V | |||
Input voltage, high (BI/TOUT) | BAT INSERT CHECK mode active | 1.2 | VCC + 0.3 | |||
VIL(CE) | Input voltage, low (CE) | VREGIN = 2.8 to 4.5 V | 0.8 | V | ||
VIH(CE) | Input voltage, high (CE) | 2.65 | ||||
Ilkg(1) | Input leakage current (I/O pins) | 0.3 | μA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIT+ | Positive-going battery voltage input at VCC | 2.05 | 2.15 | 2.20 | V | |
VHYS | Power-on reset hysteresis | 115 | mV |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
VREG25 | Regulator output voltage (VCC) | 2.8 V ≤ VREGIN ≤ 4.5V, IOUT ≤ 16 mA(1) | 2.3 | 2.5 | 2.6 | V |
2.45 V ≤ VREGIN < 2.8V (low battery), IOUT ≤ 3 mA | 2.3 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fOSC | High Frequency Oscillator | 8.389 | MHz | |||
fLOSC | Low Frequency Oscillator | 32.768 | kHz |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VADC1 | Input voltage range (TS) | VSS – 0.125 | 2 | V | ||
VADC2 | Input voltage range (BAT) | VSS – 0.125 | 5 | V | ||
VIN(ADC) | Input voltage range | 0.05 | 1 | V | ||
GTEMP | Internal temperature sensor voltage gain | –2 | mV/°C | |||
tADC_CONV | Conversion time | 125 | ms | |||
Resolution | 14 | 15 | bits | |||
VOS(ADC) | Input offset | 1 | mV | |||
ZADC1(1) | Effective input resistance (TS) | 8 | MΩ | |||
ZADC2(1) | Effective input resistance (BAT) | bq27320 not measuring cell voltage | 8 | MΩ | ||
bq27320 measuring cell voltage | 100 | kΩ | ||||
Ilkg(ADC)(1) | Input leakage current | 0.3 | μA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VSR | Input voltage range, V(SRP) and V(SRN) |
VSR = V(SRP) – V(SRN) | –0.125 | 0.125 | V | |
tSR_CONV | Conversion time | Single conversion | 1 | s | ||
Resolution | 14 | 15 | bits | |||
VOS(SR) | Input offset | 10 | μV | |||
INL | Integral nonlinearity error | ±0.007% | ±0.034% | FSR | ||
ZIN(SR)(1) | Effective input resistance | 2.5 | MΩ | |||
Ilkg(SR)(1) | Input leakage current | 0.3 | μA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tDR(1) | Data retention | 10 | Years | |||
Flash-programming write cycles(1) | 20,000 | Cycles | ||||
tWORDPROG(1) | Word programming time | 2 | ms | |||
ICCPROG(1) | Flash-write supply current | 5 | 10 | mA | ||
tDFERASE(1) | Data flash master erase time | 200 | ms | |||
tIFERASE(1) | Instruction flash master erase time | 200 | ms | |||
tPGERASE(1) | Flash page erase time | 20 | ms |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
tr | SCL/SDA rise time | 300 | ns | |||
tf | SCL/SDA fall time | 300 | ns | |||
tw(H) | SCL pulse duration (high) | 600 | ns | |||
tw(L) | SCL pulse duration (low) | 1.3 | μs | |||
tsu(STA) | Setup for repeated start | 600 | ns | |||
td(STA) | Start to first falling edge of SCL | 600 | ns | |||
tsu(DAT) | Data setup time | 100 | ns | |||
th(DAT) | Data hold time | 0 | ns | |||
tsu(STOP) | Setup time for stop | 600 | ns | |||
t(BUF) | Bus free time between stop and start | 66 | μs | |||
fSCL | Clock frequency(1) | 400 | kHz |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tc | Bit cycle time(1) | 60 | 120 | μs | ||
tWSTRB | Write start cycle(1) | 1 | 15 | μs | ||
tWDSU | Write data setup(1) | tWSTRB | 15 | μs | ||
tWDH | Write data hold(1) (2) | 60 | tc | μs | ||
trec | Recovery time(1) | 1 | μs | |||
For memory command only | 5 | |||||
tRSTRB | Read start cycle(1) | 1 | 13 | μs | ||
tODD | Output data delay(1) | tRSTRB | 13 | μs | ||
tODHO | Output data hold(1) | 17 | 60 | μs | ||
tRST | Reset time(1) | 480 | μs | |||
tPPD | Presence pulse delay(1) | 15 | 60 | μs | ||
tPP | Presence pulse(1) | 60 | 240 | μs | ||
tEPROG | EPROM programming time | 2500 | μs | |||
tPSU | Program setup time | 5 | μs | |||
tPREC | Program recovery time | 5 | μs | |||
tPRE | Program rising-edge time | 5 | μs | |||
tPFE | Program falling-edge time | 5 | μs | |||
tRSTREC | 480 | μs |