8.1 Overview

The bq27320 measures the voltage, temperature, and current to determine battery capacity and state of charge (SOC). The bq27320 monitors charge and discharge activity by sensing the voltage across a small-value resistor (5 mΩ to 20 mΩ typical) between the SRP and SRN pins and in series with the battery. By integrating charge passing through the battery, the battery’s SOC is adjusted during battery charge or discharge.

Measurements of OCV and charge integration determine chemical state of charge. The Qmax values are taken from a cell manufacturers' data sheet multiplied by the number of parallel cells. It is also used for the value in Design Capacity. It uses the OCV and Qmax value to determine StateOfCharge() on battery insertion, device reset, or on command. The FullChargeCapacity() is reported as the learned capacity available from full charge until Voltage() reaches the EDV0 threshold.

As Voltage() falls below the SysDown Set Volt Threshold, the Flags() [SYSDOWN] bit is set and SOC_INT will toggle once to provide a final warning to shut down the system. As Voltage() rises above SysDown Clear Voltage the [SYSDOWN] bit is cleared.

Additional details are found in the bq27320 Technical Reference Manual (SLUUBE6).

The fuel gauging is derived from the Compensated End of Discharge Voltage (CEDV) method, which uses a mathematical model to correlate remaining state of charge (RSOC) and voltage near to the end of discharge state. This requires a full discharge cycle for a single point FCC update. The implementation models cell voltage (OCV) as a function of battery state of charge (SOC), temperature, and current. The impedance is also a function of SOC and temperature, all of which can be satisfied by using seven parameters: EMF, C0, R0, T0, R1, TC, C1. For more detailed information, contact TI Applications Support at http://www-k.ext.ti.com/sc/technical-support/email-tech-support.asp?AAP.

8.2 Functional Block Diagram

8.3 Feature Description

The bq27320 accurately predicts the battery capacity and other operational characteristics of a single Li-based rechargeable cell. It can be interrogated by a system processor to provide cell information, such as time-to-empty (TTE) and state-of-charge (SOC) as well as SOC interrupt signal to the host.

Information is accessed through a series of commands, called Standard Commands. Further capabilities are provided by the additional Manufacturer Access Control subcommand set. Both sets of commands, indicated by the general format Command(), are used to read and write information contained within the device control and status registers, as well as its data flash locations. Commands are sent from system to gauge using the bq27320 device’s I²C serial communications engine, and can be executed during application development, system manufacture, or end-equipment operation.

Cell information is stored in the device in non-volatile flash memory. Many of these data flash locations are accessible during application development. They cannot, generally, be accessed directly during end-equipment operation. Access to these locations is achieved by either use of the bq27320 device’s companion evaluation software, through individual commands, or through a sequence of data-flash-access commands. To access a desired data flash location, the correct data flash address must be known.

The key to the bq27320 device’s high-accuracy gas gauging prediction is Texas Instruments CEDV algorithm. This algorithm uses cell measurements, characteristics, and properties to create state-of-charge predictions across a wide variety of operating conditions and over the lifetime of the battery.

The device measures charge and discharge activity by monitoring the voltage across a small-value series sense resistor (5 mΩ to 20 mΩ typical) located between the system’s V_SS and the battery’s PACK– pin. When a cell is attached to the device, FCC is learned based on cell current and on cell voltage under-loading conditions when the EDV2 threshold is reached.

The device external temperature sensing is optimized with the use of a high accuracy negative temperature coefficient (NTC) thermistor with R25 = 10.0 kΩ ±1%. B25/85 = 3435K ± 1% (such as Semitec NTC 103AT). Alternatively, the bq27320 can also be configured to use its internal temperature sensor or receive temperature data from the host processor. When an external thermistor is used, a 18.2-kΩ pull-up resistor between BI/TOUT and TS pins is also required. The bq27320 uses temperature to monitor the battery-pack environment, which is used for fuel gauging and cell protection functionality.

To minimize power consumption, the device has different power modes: NORMAL, SNOOZE, SLEEP, HIBERNATE, and BAT INSERT CHECK. The bq27320 passes automatically between these modes, depending upon the occurrence of specific events, though a system processor can initiate some of these modes directly.

For complete operational details, refer to the bq27320 Technical Reference Manual (SLUUBE6).

8.3.3 Reset and Presence Pulse

If the DATA bus is driven low for more than 120 μs, the bq27320 may be reset. Figure 6 shows that if the DATA bus is driven low for more than 480 μs, the bq27320 resets and indicates that it is ready by responding with a PRESENCE PULSE.

Figure 6. Reset Timing Diagram

8.3.4 WRITE

The WRITE bit timing diagram in Figure 7 shows that the host initiates the transmission by issuing the t_WSTRB portion of the bit and then either driving the DATA bus low for a WRITE 0, or releasing the DATA bus for a WRITE 1.

Figure 7. Write Bit Timing Diagram

8.3.5 READ

The READ bit timing diagram in Figure 8 shows that the host initiates the transmission of the bit by issuing the t_RSTRB portion of the bit. The bq27320 then responds by either driving the DATA bus low to transmit a READ 0 or releasing the DATA bus to transmit a READ 1.

Figure 8. Read Bit Timing Diagram

8.3.6 Program Pulse

Figure 9. Program Pulse Timing Diagram

8.3.8 CRC Generation

The bq27320 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the bq27320 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is: X⁸ + X⁵ + X⁴ +1.

Under certain conditions, the bq27320 also generates an 8-bit CRC value using the same polynomial function shown and provides this value to the bus master to validate the transfer of command, address, and data bytes from the bus master to the bq27320. The bq27320 computes an 8-bit CRC for the command, address, and data bytes received for the WRITE MEMORY and the WRITE STATUS commands and then outputs this value to the bus master to confirm proper transfer. Similarly, the bq27320 computes an 8-bit CRC for the command and address bytes received from the bus master for the READ MEMORY, READ STATUS, and READ DATA/GENERATE 8-BIT CRC commands to confirm that these bytes have been received correctly. The CRC generator on the bq27320 is also used to provide verification of error-free data transfer as each page of data from the 1024-bit EPROM is sent to the bus master during a READ DATA/GENERATE 8-BIT CRC command, and for the eight bytes of information in the status memory field.

In each case where a CRC is used for data transfer validation, the bus master must calculate a CRC value using the polynomial function previously given and compare the calculated value to either the 8-bit CRC value stored in the 64-bit ROM portion of the bq27320 (for ROM reads) or the 8-bit CRC value computed within the bq27320. The comparison of CRC values and decision to continue with an operation are determined entirely by the bus master. No circuitry on the bq27320 prevents a command sequence from proceeding if the CRC stored in or calculated by the bq27320 does not match the value generated by the bus master. Proper use of the CRC can result in a communication channel with a high level of integrity.

Figure 10. 8-Bit CRC Generator Circuit (X⁸ + X⁵ + X⁴ + 1)

8.3.9 Communications

8.3.9.1 I²C Interface

The bq27320 supports the standard I²C read, incremental read, quick read, one-byte write, and incremental write functions. The 7-bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as 1010101. The first 8 bits of the I²C protocol are, therefore, 0xAA or 0xAB for write or read, respectively.

The quick read returns data at the address indicated by the address pointer. The address pointer, a register internal to the I²C communication engine, increments whenever data is acknowledged by the bq27320 or the I²C master. “Quick writes” function in the same manner and are a convenient means of sending multiple bytes to consecutive command locations (such as two-byte commands that require two bytes of data).

The following command sequences are not supported:

Attempt to write a read-only address (NACK after data sent by master):

Attempt to read an address above 0x6B (NACK command):

8.3.9.2 I²C Time Out

The I²C engine releases both SDA and SCL if the I²C bus is held low for 2 seconds. If the bq27320 is holding the lines, releasing them frees them for the master to drive the lines. If an external condition is holding either of the lines low, the I²C engine enters the low-power sleep mode.

8.3.9.3 I²C Command Waiting Time

To ensure proper operation at 400 kHz, a t_(BUF) ≥ 66 μs bus-free waiting time must be inserted between all packets addressed to the bq27320. In addition, if the SCL clock frequency (f_SCL) is > 100 kHz, use individual 1-byte write commands for proper data flow control. The following diagram shows the standard waiting time required between issuing the control subcommand the reading the status result. For read-write standard command, a minimum of 2 seconds is required to get the result updated. For read-only standard commands, there is no waiting time required, but the host must not issue any standard command more than two times per second. Otherwise, the gauge could result in a reset issue due to the expiration of the watchdog timer.

8.3.9.4 I²C Clock Stretching

A clock stretch can occur during all modes of fuel gauge operation. In SNOOZE and HIBERNATE modes, a short clock stretch occurs on all I²C traffic as the device must wake-up to process the packet. In the other modes (BAT INSERT CHECK, NORMAL) clock stretching only occurs for packets addressed for the fuel gauge. The majority of clock stretch periods are small as the I²C interface performs normal data flow control. However, less frequent yet more significant clock stretch periods may occur as blocks of data flash are updated. The following table summarizes the approximate clock stretch duration for various fuel gauge operating conditions.

Gauging Mode	Operating Condition/Comment	Approximate Duration
SLEEP HIBERNATE	Clock stretch occurs at the beginning of all traffic as the device wakes up.	≤ 4 ms
BAT INSERT CHECK NORMAL	Clock stretch occurs within the packet for flow control (after a start bit, ACK or first data bit).	≤ 4 ms
	Data flash block writes.	72 ms
	Restored data flash block write after loss of power.	116 ms

8.4 Device Functional Modes

To minimize power consumption, the device has different power modes: NORMAL, SNOOZE, SLEEP, HIBERNATE, and BAT INSERT CHECK. The bq27320 passes automatically between these modes, depending upon the occurrence of specific events, though a system processor can initiate some of these modes directly.

• In NORMAL mode, the gas gauge is fully powered and can execute any allowable task.
• In SNOOZE mode, low-frequency and high-frequency oscillators are active. Although the SNOOZE mode has higher current consumption than the SLEEP mode, it is also a reduced power mode.
• In SLEEP mode, the gas gauge turns off the high-frequency oscillator and exists in a reduced-power state, periodically taking measurements and performing calculations.
• In HIBERNATE mode, the gas gauge is in a low-power state, but can be woken up by communication or certain IO activity.
• BAT INSERT CHECK mode is a powered up, but low-power halted, state, where the gas gauge resides when no battery is inserted into the system.