SLUSBN7D January   2014  – April 2017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current
    6. 7.6  Digital Input and Output DC Characteristics
    7. 7.7  LDO Regulator, Wake-Up, and Auto-Shutdown DC Characteristics
    8. 7.8  ADC (Temperature and Cell Measurement) Characteristics
    9. 7.9  Integrating ADC (Coulomb Counter) Characteristics
    10. 7.10 I2C-Compatible Interface Communication Timing Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Standard Data Commands
      2. 8.5.2 Control(): 0x00 and 0x01
      3. 8.5.3 Extended Data Commands
      4. 8.5.4 Communications
        1. 8.5.4.1 I2C Interface
        2. 8.5.4.2 I2C Time Out
        3. 8.5.4.3 I2C Command Waiting Time
        4. 8.5.4.4 I2C Clock Stretching
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 High-Side or Low-Side Sense Resistor
        2. 9.2.2.2 BAT Voltage Sense Input
        3. 9.2.2.3 Sense Resistor Selection
        4. 9.2.2.4 Communication Interface Lines
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendation
    1. 10.1 Power Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
      2. 12.1.2 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VBAT BAT pin input voltage range –0.3 6 V
VSR SRP and SRN pins input voltage range –0.3 VBAT + 0.3 V
Differential voltage across SRP and SRN. ABS(SRP–SRN) 2 V
VDD VDD pin supply voltage range (LDO output) –0.3 2 V
VIOD Open-drain IO pins (SDA, SCL) –0.3 6 V
VPROG PROG (pin 12) –0.3 7.8 V
VIOPP Push-pull IO pins (TEST, pin 10) –0.3 VDD + 0.3 V
TA Operating free-air temperature range –40 85 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

TA = 30°C and VREGIN = VBAT = 3.6 V (unless otherwise noted)
MIN NOM MAX UNIT
CBAT(1) External input capacitor for internal LDO between BAT and VSS Nominal capacitor values specified. Recommend a 5% ceramic X5R type capacitor located close to the device. 0.1 μF
CLDO18(1) External output capacitor for internal LDO between VDD and VSS 0.47 μF
VPU(1) External pull-up voltage for open-drain pins (SDA, SCL, PROG) 1.62 3.6 V
VPV PROG Programming Voltage [RA0] TA = 15°C to 35°C. OTP Programming mode only. 7.3 7.4 7.5 V
IPV PROG Programming Current [RA0] 4 5 mA
(1) Specified by design. Not production tested.

7.4 Thermal Information

THERMAL METRIC(1) bq27411-G1 UNIT
DRZ (12 PINS)
RθJA Junction-to-ambient thermal resistance 64.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 59.8
RθJB Junction-to-board thermal resistance 52.7
ψJT Junction-to-top characterization parameter 0.3
ψJB Junction-to-board characterization parameter 28.3
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics Application Report, SPRA953.

7.5 Supply Current

TA = 30°C and VREGIN = VBAT = 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC(1) NORMAL mode current ILOAD > Sleep Current(2) 93 μA
ISLP(1) SLEEP mode current ILOAD < Sleep Current(2) 21 μA
IHIB(1) HIBERNATE mode current ILOAD < Hibernate Current(2) 9 μA
ISD(1) SHUTDOWN mode current Fuel gauge in host-commanded SHUTDOWN mode.
(LDO regulator output disabled) 		0.6 μA
(1) Specified by design. Not production tested.
(2) Wake Comparator Disabled

7.6 Digital Input and Output DC Characteristics

TA = –40°C to 85°C, typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH(OD)(Force Note1)(1) Input voltage, high(2) External pullup resistor to VPU VPU × 0.7 V
VIH(PP) Input voltage, high(3) 1.4 V
VIL Input voltage, low(2)(3) 0.6 V
VOL Output voltage, low(2) 0.6 V
IOH Output source current, high(2) 0.5 mA
IOL(OD) Output sink current, low(2) –3 mA
CIN(1) Input capacitance(2)(3) 5 pF
Ilkg Input leakage current(2)(3) SCL, SDA, and TEST pins 0.1 μA
PROG pin 1.0
(1) Specified by design. Not production tested.
(2) Open Drain pins: (SCL, SDA, PROG)
(3) Push-pull pin: (TEST)

7.7 LDO Regulator, Wake-Up, and Auto-Shutdown DC Characteristics

TA = –40°C to 85°C, typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)(Force Note1)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBAT BAT pin regulator input 2.45 4.5 V
VDD Regulator output voltage 1.8 V
UVLOIT+ VBAT Undervoltage lockout
LDO Wake-up rising threshold		 2 V
UVLOIT– VBAT Undervoltage lockout
LDO Auto-shutdown falling threshold		 1.95 V
(1) Specified by design. Not production tested.

7.8 ADC (Temperature and Cell Measurement) Characteristics

TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted) (Force Note1)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN(BAT) BAT pin voltage measurement range Voltage divider enabled 2.45 4.5 V
tADC_CONV Conversion time 125 ms
Effective Resolution 15 bits
(1) Specified by design. Not tested in production.

7.9 Integrating ADC (Coulomb Counter) Characteristics

TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)(Force Note1)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSR Input voltage range from BAT to SRX pins BAT ± 25 mV
tSR_CONV Conversion time Single conversion 1 s
Effective Resolution Single conversion 16 bits
(1) Specified by design. Not tested in production.

7.10 I2C-Compatible Interface Communication Timing Characteristics

TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)
MIN TYP MAX UNIT
Standard Mode (100 kHz)
td(STA) (Force Note1)(1) Start to first falling edge of SCL 4 μs
tw(L) SCL pulse duration (low) 4.7 μs
tw(H) SCL pulse duration (high) 4 μs
tsu(STA) Setup for repeated start 4.7 μs
tsu(DAT) Data setup time Host drives SDA 250 ns
th(DAT) Data hold time Host drives SDA 0 ns
tsu(STOP) Setup time for stop 4 μs
t(BUF) Bus free time between stop and start Includes command waiting time 66 μs
tf SCL or SDA fall time (1) 300 ns
tr SCL or SDA rise time (1) 300 ns
fSCL Clock frequency(2) 100 kHz
Fast Mode (400 kHz)
td(STA) Start to first falling edge of SCL 600 ns
tw(L) SCL pulse duration (low) 1300 ns
tw(H) SCL pulse duration (high) 600 ns
tsu(STA) Setup for repeated start 600 ns
tsu(DAT) Data setup time Host drives SDA 100 ns
th(DAT) Data hold time Host drives SDA 0 ns
tsu(STOP) Setup time for stop 600 ns
t(BUF) Bus free time between stop and start Includes command waiting time 66 μs
tf SCL or SDA fall time (1) 300 ns
tr SCL or SDA rise time (1) 300 ns
fSCL Clock frequency(2) 400 kHz
(1) Specified by design. Not production tested.
(2) If the clock frequency (fSCL) is > 100 kHz, use 1-byte write commands for proper operation. All other transactions types are supported at 400 kHz. (See I2C Interface and I2C Command Waiting Time.)
bq27411-G1 tim_dia_i2c.gif Figure 1. I2C-Compatible Interface Timing Diagrams

7.11 Typical Characteristics

bq27411-G1 D003_SLUSBH1.gif Figure 2. Voltage Accuracy
bq27411-G1 D002_SLUSBH1.gif Figure 4. Current Accuracy
bq27411-G1 D001_SLUSBH1.gif Figure 3. Temperature Accuracy