The bq27532-G1 system-side, Li-Ion battery management unit is a microcontroller peripheral that provides Impedance Track™ fuel gauging and charging control for single-cell Li-Ion battery packs. The fuel gauge requires little system microcontroller firmware development. Together with bq2425x single-cell switch-mode charger, the fuel gauge manages an embedded battery (non-removable) or a removable battery pack.
The fuel gauge uses the patented Impedance Track algorithm for fuel gauging, and provides information, such as remaining battery capacity (mAh), state-of-charge (%), runtime-to-empty (minimum), battery voltage (mV), temperature (°C), and SoH (%).
Battery fuel gauging with the device requires only PACK+ (P+), PACK– (P–), and thermistor (T) connections to a removable battery pack or embedded battery circuit. The 15-pin NanoFree™ (CSP) package has dimensions of 2.61 mm × 1.96 mm with 0.5-mm lead pitch. It is ideal for space-constrained applications.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
bq27532-G1 | CSP (15) | 2.61 mm × 1.96 mm |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
BAT | E2 | I | Cell-voltage measurement input. ADC input. TI recommends 4.8 V maximum for conversion accuracy. |
BI/TOUT | E3 | IO | Battery-insertion detection input. Power pin for pack thermistor network. Thermistor-multiplexer control pin. Use with pullup resistor > 1 MΩ (1.8 MΩ typical). |
BSCL | B2 | O | Battery charger clock output line for chipset communication. Use without external pullup resistor. Push-pull output. |
BSDA | C3 | IO | Battery charger data line for chipset communication. Use without external pullup resistor. Push-pull output. |
CE | D2 | I | Chip enable. Internal LDO is disconnected from REGIN when driven low. Note: CE has an internal ESD protection diode connected to REGIN. TI recommends maintaining VCE ≤ VREGIN under all conditions. |
REGIN | E1 | P | Regulator input. Decouple with 0.1-μF ceramic capacitor to VSS. |
SCL | A3 | I | Slave I2C serial communications clock input line for communication with system (master). Open-drain IO. Use with 10-kΩ pullup resistor (typical). |
SDA | B3 | IO | Slave I2C serial communications data line for communication with system (master). Open-drain IO. Use with 10-kΩ pullup resistor (typical). |
SOC_INT | A2 | IO | SOC state interrupts output. Generates a pulse as described in bq27532-G1 Technical Reference Manual, SLUUB04. Open-drain output. |
SRN | B1 | AI | Analog input pin connected to the internal coulomb counter where SRN is nearest the VSS connection. Connect to 5- to 20-mΩ sense resistor. |
SRP | A1 | AI | Analog input pin connected to the internal coulomb counter where SRP is nearest the PACK– connection. Connect to 5- to 20-mΩ sense resistor. |
TS | D3 | AI | Pack thermistor voltage sense (use 103AT-type thermistor). ADC input. |
VCC | D1 | P | Regulator output and bq27532-G1 device power. Decouple with 1-μF ceramic capacitor to VSS. Pin is not intended to power additional external loads. |
VSS | C1, C2 | P | Device ground |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VREGIN | Regulator input | –0.3 | 5.5 | V |
–0.3 | 6 (2) | V | ||
VCE | CE input pin | –0.3 | VREGIN + 0.3 | V |
VCC | Supply voltage | –0.3 | 2.75 | V |
VIOD | Open-drain IO pins (SDA, SCL, SOC_INT) | –0.3 | 5.5 | V |
VBAT | BAT input pin | –0.3 | 5.5 | V |
–0.3 | 6 (2) | V | ||
VI | Input voltage to all other pins (BI/TOUT, TS, SRP, SRN, BSCL, BSDA) |
–0.3 | VCC + 0.3 | V |
TA | Operating free-air temperature | –40 | 85 | °C |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, BAT pin(1) | ±1500 | V |
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, All other pins(1) | ±2000 | |||
Charged device model(CDM), per JEDEC specification JESD22-C101(2) | ±250 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VREGIN | Supply voltage | No operating restrictions | 2.8 | 4.5 | V | |
No flash writes | 2.45 | 2.8 | ||||
CREGIN | External input capacitor for internal LDO between REGIN and VSS | Nominal capacitor values specified. Recommend a 5% ceramic X5R-type capacitor located close to the device. | 0.1 | μF | ||
CLDO25 | External output capacitor for internal LDO between VCC and VSS | 0.47 | 1 | μF | ||
tPUCD | Power-up communication delay | 250 | ms |
THERMAL METRIC(1) | bq27532-G1 | UNIT | |
---|---|---|---|
YZF (CSP) | |||
15 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 70 | °C/W |
RJC(top) | Junction-to-case (top) thermal resistance | 17 | °C/W |
RθJB | Junction-to-board thermal resistance | 20 | °C/W |
ψJT | Junction-to-top characterization parameter | 1 | °C/W |
ψJB | Junction-to-board characterization parameter | 18 | °C/W |
RθJC(bottom) | Junction-to-case (bottom) thermal resistance | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ICC (1) | Normal operating-mode current | Fuel gauge in NORMAL mode ILOAD > Sleep current |
118 | μA | ||
ISLP+ (1) | Sleep+ operating-mode current | Fuel gauge in SLEEP+ mode ILOAD < Sleep current |
62 | μA | ||
ISLP (1) | Low-power storage-mode current | Fuel gauge in SLEEP mode ILOAD < Sleep current |
23 | μA | ||
IHIB (1) | Hibernate operating-mode current | Fuel gauge in HIBERNATE mode ILOAD < Hibernate current |
8 | μA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VOL | Output voltage, low (SCL, SDA, SOC_INT, BSDA, BSCL) | IOL = 3 mA | 0.4 | V | ||
VOH(PP) | Output voltage, high (BSDA, BSCL) | IOH = –1 mA | VCC – 0.5 | V | ||
VOH(OD) | Output voltage, high (SDA, SCL, SOC_INT) | External pullup resistor connected to VCC | VCC – 0.5 | |||
VIL | Input voltage, low (SDA, SCL) | –0.3 | 0.6 | V | ||
Input voltage, low (BI/TOUT) | BAT INSERT CHECK MODE active | –0.3 | 0.6 | |||
VIH | Input voltage, high (SDA, SCL) | 1.2 | V | |||
Input voltage, high (BI/TOUT) | BAT INSERT CHECK MODE active | 1.2 | VCC + 0.3 | |||
VIL(CE) | Input voltage, low (CE) | VREGIN = 2.8 to 4.5 V | 0.8 | V | ||
VIH(CE) | Input voltage, high (CE) | 2.65 | ||||
Ilkg (1) | Input leakage current (IO pins) | 0.3 | μA |
PARAMETER | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
VIT+ | Positive-going battery voltage input at VCC | 2.05 | 2.15 | 2.20 | V | |
VHYS | Power-on reset hysteresis | 115 | mV |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
VREG25 | Regulator output voltage (VCC) | 2.8 V ≤ VREGIN ≤ 4.5 V, IOUT ≤ 16 mA(1) | 2.3 | 2.5 | 2.6 | V |
2.45 V ≤ VREGIN < 2.8 V (low battery), IOUT ≤ 3 mA |
2.3 | V |
PARAMETER | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
fOSC | High-frequency oscillator | 8.389 | MHz | |||
fLOSC | Low-frequency oscillator | 32.768 | kHz |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VADC1 | Input voltage range (TS) | VSS – 0.125 | 2 | V | ||
VADC2 | Input voltage range (BAT) | VSS – 0.125 | 5 | V | ||
VIN(ADC) | Input voltage range | 0.05 | 1 | V | ||
GTEMP | Internal temperature sensor voltage gain | –2 | mV/°C | |||
tADC_CONV | Conversion time | 125 | ms | |||
Resolution | 14 | 15 | bits | |||
VOS(ADC) | Input offset | 1 | mV | |||
ZADC1 (1) | Effective input resistance (TS) | 8 | MΩ | |||
ZADC2 (1) | Effective input resistance (BAT) | Device not measuring cell voltage | 8 | MΩ | ||
Device measuring cell voltage | 100 | kΩ | ||||
Ilkg(ADC) (1) | Input leakage current | 0.3 | μA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VSR | Input voltage range, V(SRP) and V(SRN) |
VSR = V(SRP) – V(SRN) | –0.125 | 0.125 | V | |
tSR_CONV | Conversion time | Single conversion | 1 | s | ||
Resolution | 14 | 15 | bits | |||
VOS(SR) | Input offset | 10 | μV | |||
INL | Integral nonlinearity error | ±0.007% | ±0.034% | FSR | ||
ZIN(SR) (1) | Effective input resistance | 2.5 | MΩ | |||
Ilkg(SR)(1) | Input leakage current | 0.3 | μA |
PARAMETER | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
tDR (1) | Data retention | 10 | Years | |||
Flash-programming write cycles(1) | 20,000 | Cycles | ||||
tWORDPROG (1) | Word programming time | 2 | ms | |||
ICCPROG (1) | Flash-write supply current | 5 | 10 | mA | ||
tDFERASE (1) | Data flash master erase time | 200 | ms | |||
tIFERASE (1) | Instruction flash master erase time | 200 | ms | |||
tPGERASE (1) | Flash page erase time | 20 | ms |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
tr | SCL or SDA rise time | 300 | ns | ||
tf | SCL or SDA fall time | 300 | ns | ||
tw(H) | SCL pulse duration (high) | 600 | ns | ||
tw(L) | SCL pulse duration (low) | 1.3 | μs | ||
tsu(STA) | Setup for repeated start | 600 | ns | ||
td(STA) | Start to first falling edge of SCL | 600 | ns | ||
tsu(DAT) | Data setup time | 100 | ns | ||
th(DAT) | Data hold time | 0 | ns | ||
tsu(STOP) | Setup time for stop | 600 | ns | ||
t(BUF) | Bus free time between stop and start | 66 | μs | ||
fSCL | Clock frequency (1) | 400 | kHz |