SLUSC53B May 2015 – May 2018
PRODUCTION DATA.
Some bq27546-G1 algorithm settings are configured via the Pack Configuration C data flash register, as indicated in Table 11. This register is programmed/read via the methods described in the bq27546-G1 Technical Reference Manual (SLUUB74). The register is located at Subclass = 64, offset = 3.
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | |
---|---|---|---|---|---|---|---|---|
RSVD | RSVD | RelaxRCJumpOK | SmoothEn | SleepWk
Chg |
RSVD | RSVD | RSVD | |
Default = | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 |
0x18 |
RSVD = | Reserved. Must be 0. |
RelaxRCJumpOK = | Allow SOC to change due to temperature change during relaxation when SOC smoothing algorithm is enabled. True when set. |
SmoothEn = | Enable SOC smoothing algorithm. True when set. |
SleepWkChg = | Enables compensation for the passed charge missed when waking from SLEEP mode. |