SLUSBV9D March   2014  – January 2018

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power-On Reset
    6. 6.6  2.5-V LDO Regulator
    7. 6.7  Charger Attachment and Removal Detection
    8. 6.8  CHG and DSG FET Drive
    9. 6.9  Overvoltage Protection (OVP)
    10. 6.10 Undervoltage Protection (UVP)
    11. 6.11 Overcurrent in Discharge (OCD)
    12. 6.12 Overcurrent in Charge (OCC)
    13. 6.13 Short-Circuit in Discharge (SCD)
    14. 6.14 Low Voltage Charging
    15. 6.15 Internal Temperature Sensor Characteristics
    16. 6.16 High-Frequency Oscillator
    17. 6.17 Low-Frequency Oscillator
    18. 6.18 Integrating ADC (Coulomb Counter) Characteristics
    19. 6.19 ADC (Temperature and Cell Voltage) Characteristics
    20. 6.20 Data Flash Memory Characteristics
    21. 6.21 Timing Requirements
    22. 6.22 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Configuration
      2. 7.3.2 Fuel Gauging
      3. 7.3.3 Power Modes
        1. 7.3.3.1 NORMAL Mode
        2. 7.3.3.2 SLEEP Mode
        3. 7.3.3.3 FULLSLEEP Mode
      4. 7.3.4 Li-Ion Battery Protector Description
        1. 7.3.4.1 High-Side NFET Charge and Discharge FET Drive
        2. 7.3.4.2 Protector Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
        1. 7.4.1.1 NORMAL Mode
        2. 7.4.1.2 OVERVOLTAGE Mode
        3. 7.4.1.3 UNDERVOLTAGE Mode
        4. 7.4.1.4 OVERCURRENT IN CHARGE Mode
        5. 7.4.1.5 OVERCURRENT IN DISCHARGE and SHORT-CIRCUIT IN DISCHARGE Mode
        6. 7.4.1.6 SHUTDOWN WAIT Mode
          1. 7.4.1.6.1 ANALOG SHUTDOWN State
        7. 7.4.1.7 LOW VOLTAGE CHARGING State
      2. 7.4.2 Firmware Control of Protector
      3. 7.4.3 OVERTEMPERATURE FAULT Mode
      4. 7.4.4 Wake-Up Comparator
    5. 7.5 Battery Parameter Measurements
      1. 7.5.1 Charge and Discharge Counting
      2. 7.5.2 Voltage
      3. 7.5.3 Current
      4. 7.5.4 Auto-Calibration
      5. 7.5.5 Temperature
    6. 7.6 Communications
      1. 7.6.1 HDQ Single-Pin Serial Interface
      2. 7.6.2 I2C Interface
        1. 7.6.2.1 I2C Time Out
        2. 7.6.2.2 I2C Command Waiting Time
    7. 7.7 Standard Data Commands
      1. 7.7.1 Control(): 0x00 and 0x01
    8. 7.8 Extended Data Commands
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Pack-Side, Single-Cell Li-Ion Fuel Gauge and Protector
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1  BAT Voltage Sense Input
        2. 8.2.3.2  SRP and SRN Current Sense Inputs
        3. 8.2.3.3  Sense Resistor Selection
        4. 8.2.3.4  TS Temperature Sense Input
        5. 8.2.3.5  Thermistor Selection
        6. 8.2.3.6  VPWR Power Supply Input Filtering
        7. 8.2.3.7  REG25 LDO Output Filtering
        8. 8.2.3.8  Communication Interface Lines
        9. 8.2.3.9  PACKP Voltage Sense Input
        10. 8.2.3.10 CHG and DSG Charge Pump Voltage Outputs
        11. 8.2.3.11 NFET Selection
        12. 8.2.3.12 Additional ESD Protection Components
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendation
    1. 9.1 Power Supply Decoupling
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Li-Ion Cell Connections
      2. 10.1.2 Sense Resistor Connections
      3. 10.1.3 Thermistor Connections
      4. 10.1.4 FET Connections
      5. 10.1.5 ESD Component Connections
      6. 10.1.6 High Current and Low Current Path Separation
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receive Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.3.11 NFET Selection

The choice in NFETs for a single-cell battery pack design will depend on a variety of factors including package type, size, and device cost as well as performance metrics such as drain-to-source resistance (rDS(on)), gate capacitance, maximum current and power handling, and similar. At a bare minimum, it is recommended that the selected FETs have a drain-to-source voltage (VDS) and gate-to-source (VGS) voltage tolerance of 12 V. Some FETs can are designed to handle as much as 24 V between the drain and source terminals and this would provide an increased safety margin for the pack design. Further, the DC current rating should be high enough to safely handle sustained current in charge or discharge direction just below the maximum threshold tolerances of the configured OCC and OCD protections and the lowest possible sense resistance value based on tolerance and TCR considerations, or vice-versa. This ensures that there is sufficient power dissipation margin given a worst case scenario for the fault detections. In addition, striving for minimal FET resistance at the expected gate bias as well as lowest gate capacitance will help reduce conduction losses and increase power efficiency as well as achieve faster turn-on and turn-off times for the FETs. Many of these FETs are now offered as dual, back-back NFETs in wafer-chip scale (WCSP) packaging, decreasing both BOM count and shrinking necessary board real estate to accommodate the components. Last, one should always refer to the safe operating area (SOA) curves of the target FETs to ensure that the boundaries are never violated based on all possible load conditions in the end application. The CSD83325L is an excellent example of a FET solution that meets all of the aforementioned criteria, offering rDS(on) of 10.3 mΩ and VDS of 12 V with back-to-back NFETs in a chip-scale package, a perfect fit for battery pack designs.