SLUSDH5B March 2019 – December 2022 BQ27Z561-R1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
fSCL | Clock operating frequency | SCL duty cycle = 50% | 400 | kHz | ||
tHD:STA | START condition hold time | 0.6 | µs | |||
tLOW | Low period of the SCL Clock | 1.3 | µs | |||
tHIGH | High period of the SCL Clock | 600 | ns | |||
tSU:STA | Setup repeated START | 600 | ns | |||
tHD:DAT | Data hold time (SDA input) | 0 | ns | |||
tSU:DAT | Data setup time (SDA input) | 100 | ns | |||
tr | Clock rise time | 10% to 90% | 300 | ns | ||
tf | Clock fall time | 90% to 10% | 300 | ns | ||
tSU:STO | Setup time STOP condition | 0.6 | µs | |||
tBUF | Bus free time STOP to START | 1.3 | µs |