SLUSE22B February   2020  – November 2022 BQ27Z561-R2

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current
    6. 7.6  Internal 1.8-V LDO (REG18)
    7. 7.7  I/O (PULS, INT)
    8. 7.8  Chip Enable (CE)
    9. 7.9  Internal Temperature Sensor
    10. 7.10 NTC Thermistor Measurement Support
    11. 7.11 Coulomb Counter (CC)
    12. 7.12 Analog Digital Converter (ADC)
    13. 7.13 Internal Oscillator Specifications
    14. 7.14 Voltage Reference1 (REF1)
    15. 7.15 Voltage Reference2 (REF2)
    16. 7.16 Flash Memory
    17. 7.17 I2C I/O
    18. 7.18 I2C Timing — 100 kHz
    19. 7.19 I2C Timing — 400 kHz
    20. 7.20 HDQ Timing
    21. 7.21 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  BQ27Z561-R2 Processor
      2. 8.3.2  Battery Parameter Measurements
        1. 8.3.2.1 Coulomb Counter (CC)
        2. 8.3.2.2 CC Digital Filter
        3. 8.3.2.3 ADC Multiplexer
        4. 8.3.2.4 Analog-to-Digital Converter (ADC)
        5. 8.3.2.5 Internal Temperature Sensor
        6. 8.3.2.6 External Temperature Sensor Support
      3. 8.3.3  Power Supply Control
      4. 8.3.4  Bus Communication Interface
      5. 8.3.5  Low Frequency Oscillator
      6. 8.3.6  High Frequency Oscillator
      7. 8.3.7  1.8-V Low Dropout Regulator
      8. 8.3.8  Internal Voltage References
      9. 8.3.9  Gas Gauging
      10. 8.3.10 Charge Control Features
      11. 8.3.11 Authentication
    4. 8.4 Device Functional Modes
      1. 8.4.1 Lifetime Logging Features
      2. 8.4.2 Configuration
        1. 8.4.2.1 Coulomb Counting
        2. 8.4.2.2 Cell Voltage Measurements
        3. 8.4.2.3 Auto Calibration
        4. 8.4.2.4 Temperature Measurements
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements (Default)
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Changing Design Parameters
      3. 9.2.3 Calibration Process
      4. 9.2.4 Gauging Data Updates
        1. 9.2.4.1 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.20 HDQ Timing

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tB Break time 190 µs
tBR Break recovery time 40 µs
tHW1 Host write 1 time Host drives HDQ 0.5 50 µs
tHW0 Host write 0 time Host drives HDQ 86 145 µs
tCYCH Cycle time, host to device Device drives HDQ 190 µs
tCYCD Cycle time, device to Host Device drives HDQ 190 205 250 µs
tDW1 Device write 1 time Device drives HDQ 32 50 µs
tDW0 Device write 0 time Device drives HDQ 80 145 µs
tRSPS Device response time Device drives HDQ 190 950 µs
tTRND Host turn around time Host drives HDQ after device drives HDQ 250 µs
tRISE HDQ line rising time to logic 1 1.8 µs
tRST HDQ Reset Host drives HDQ low before device reset 2.2 s
GUID-84DD0DBB-0C69-4BA8-8F76-D9C5F8223F32-low.gifFigure 7-1 I2C Timing
GUID-3A2F0A25-05BB-490B-A0EF-F03CBB0C5379-low.gifFigure 7-2 HDQ Timing