SLUSDW2A November   2021  – February 2022 BQ27Z746

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 Supply Current
      2. 6.5.2 Common Analog (LDO, LFO, HFO, REF1, REF2, I-WAKE)
      3. 6.5.3 Battery Protection (CHG, DSG)
      4. 6.5.4 Cell Sensing Output (BAT_SP, BAT_SN)
      5. 6.5.5 Gauge Measurements (ADC, CC, Temperature)
      6. 6.5.6 Flash Memory
    6. 6.6 Digital I/O: DC Characteristics
    7. 6.7 Digital I/O: Timing Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  BQ27Z746 Processor
      2. 7.3.2  Battery Parameter Measurements
        1. 7.3.2.1 Coulomb Counter (CC) and Digital Filter
        2. 7.3.2.2 ADC Multiplexer
        3. 7.3.2.3 Analog-to-Digital Converter (ADC)
        4. 7.3.2.4 Internal Temperature Sensor
        5. 7.3.2.5 External Temperature Sensor Support
      3. 7.3.3  Power Supply Control
      4. 7.3.4  Bus Communication Interface
      5. 7.3.5  Low Frequency Oscillator
      6. 7.3.6  High Frequency Oscillator
      7. 7.3.7  1.8-V Low Dropout Regulator
      8. 7.3.8  Internal Voltage References
      9. 7.3.9  Overcurrent in Discharge Protection
      10. 7.3.10 Overcurrent in Charge Protection
      11. 7.3.11 Short-Circuit Current in Discharge Protection
      12. 7.3.12 Primary Protection Features
      13. 7.3.13 Battery Sensing
      14. 7.3.14 Gas Gauging
      15. 7.3.15 Zero Volt Charging (ZVCHG)
      16. 7.3.16 Charge Control Features
      17. 7.3.17 Authentication
    4. 7.4 Device Functional Modes
      1. 7.4.1 Lifetime Logging Features
      2. 7.4.2 Configuration
        1. 7.4.2.1 Coulomb Counting
        2. 7.4.2.2 Cell Voltage Measurements
        3. 7.4.2.3 Auto Calibration
        4. 7.4.2.4 Temperature Measurements
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Default)
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Changing Design Parameters
      3. 8.2.3 Calibration Process
      4. 8.2.4 Gauging Data Updates
        1. 8.2.4.1 Application Curve
  9. 9 Power Supply Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Orderable, and Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YAH|15
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.15 Zero Volt Charging (ZVCHG)

ZVCHG (0-V charging) is a special function that allows charging a severely depleted battery that is below the FET driver charge pump shutdown voltage (VFET_SHUT). The BQ27Z746 has ZVCHG enabled. If VBAT > V0INH and VBAT < VFET_SHUT and the charger voltage at PACK+ is > V0CHGR, then the CHG output will be driven to the voltage of the PACK pin, allowing charging. ZVCHG mode in the BQ27Z746 is exited when VBAT > VFET_SHUT_REL, at which point the charge pump is enabled, and CHG transitions to being driven by the charge pump. For BQ27Z746, when the voltage on VDD is below V0INH, the CHG output becomes high impedance, and any leakage current flowing through the CHG FET may cause this voltage to rise and reenable charging. If this is undesired, a high impedance resistor can be included between the CHG FET gate and source to overcome any leakage and ensure the FET remains disabled in this case. This resistance should be as high as possible while still ensuring the FET is disabled, since it will increase the device operating current when the CHG driver is enabled. Because gate leakage is typically extremely low, a gate-source resistance of 50 MΩ to 100 MΩ may be sufficient to overcome the leakage.