SLUSDW2A November   2021  – February 2022 BQ27Z746

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 Supply Current
      2. 6.5.2 Common Analog (LDO, LFO, HFO, REF1, REF2, I-WAKE)
      3. 6.5.3 Battery Protection (CHG, DSG)
      4. 6.5.4 Cell Sensing Output (BAT_SP, BAT_SN)
      5. 6.5.5 Gauge Measurements (ADC, CC, Temperature)
      6. 6.5.6 Flash Memory
    6. 6.6 Digital I/O: DC Characteristics
    7. 6.7 Digital I/O: Timing Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  BQ27Z746 Processor
      2. 7.3.2  Battery Parameter Measurements
        1. 7.3.2.1 Coulomb Counter (CC) and Digital Filter
        2. 7.3.2.2 ADC Multiplexer
        3. 7.3.2.3 Analog-to-Digital Converter (ADC)
        4. 7.3.2.4 Internal Temperature Sensor
        5. 7.3.2.5 External Temperature Sensor Support
      3. 7.3.3  Power Supply Control
      4. 7.3.4  Bus Communication Interface
      5. 7.3.5  Low Frequency Oscillator
      6. 7.3.6  High Frequency Oscillator
      7. 7.3.7  1.8-V Low Dropout Regulator
      8. 7.3.8  Internal Voltage References
      9. 7.3.9  Overcurrent in Discharge Protection
      10. 7.3.10 Overcurrent in Charge Protection
      11. 7.3.11 Short-Circuit Current in Discharge Protection
      12. 7.3.12 Primary Protection Features
      13. 7.3.13 Battery Sensing
      14. 7.3.14 Gas Gauging
      15. 7.3.15 Zero Volt Charging (ZVCHG)
      16. 7.3.16 Charge Control Features
      17. 7.3.17 Authentication
    4. 7.4 Device Functional Modes
      1. 7.4.1 Lifetime Logging Features
      2. 7.4.2 Configuration
        1. 7.4.2.1 Coulomb Counting
        2. 7.4.2.2 Cell Voltage Measurements
        3. 7.4.2.3 Auto Calibration
        4. 7.4.2.4 Temperature Measurements
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Default)
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Changing Design Parameters
      3. 8.2.3 Calibration Process
      4. 8.2.4 Gauging Data Updates
        1. 8.2.4.1 Application Curve
  9. 9 Power Supply Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Orderable, and Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YAH|15
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5.2 Common Analog (LDO, LFO, HFO, REF1, REF2, I-WAKE)

Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal 1.8-V LDO (REG18)
VREG18 Regulator output voltage 1.6 1.8 2.0 V
ΔVREG18TEMP Regulator output change with temperature ΔVBAT/ΔTA, IREG18 = 10 mA –1.2% +1.2%
ΔVREG18LINE Line regulation –0.8% 0.8%
ΔVREG18LOAD Load regulation IREG18 = 16 mA –1.5% 1.5%
ISHORT Short Circuit Current Limit VREG18 = 0 V 18 60 mA
PSRRREG18 Power Supply Rejection Ratio ΔVBAT/ΔVREG18, IREG18 = 10 mA, VBAT > 2.5 V, f = 10 Hz 50 dB
VPORth POR threshold Rising Threshold 1.55 1.65 1.75 V
VPORhy POR hysteresis 0.1 V
VENAB ENAB turn-on voltage for LDO (1) Active low falling threshold 0.4 V
RENAB ENAB pin pullup resistance (1) Internal pull-up to VDD 0.7 1 1.3 MΩ
Low Frequency Internal Oscillator (LFO)
fLFO LFO Operating frequency Normal operating mode 65.536 kHz
fLFO(ERR) LFO Frequency error –2.5% +2.5%
fLFO32 LFO operating frequency Low power mode 32.768 kHz
fLFO32(ERR) LFO frequency error –5% +5%
High Frequency Internal Oscillator (HFO)
fHFO HFO operating frequency 16.78 MHz
fHFO(ERR) HFO frequency error TA = –20°C to 70°C –2.5% 2.5%
TA = –40°C to 85°C –3.5% 3.5%
tHFOSTART HFO start-up time TA = –40°C to 85°C, CLKCTL[HFRAMP] = 1, oscillator frequency within +/- 3% of nominal frequency or a power-on reset 4 ms
Voltage Reference1 (VREF1)
VREF1 Internal reference voltage REF1 is for protection circuits, LDO, and CC 1.195 1.21 1.227 V
VREF1_DRIFT Internal Reference Voltage Drift –80 +80 PPM/°C
Voltage Reference2 (VREF2)
VREF2 Internal Reference Voltage REF2 is for the ADC 1.2 1.21 1.22 V
VREF2_DRIFT Internal Reference Voltage Drift –20 +20 PPM/°C
Wake-Up Comparator (I-WAKE)
VWAKE Sense resistor voltage threshold range to wake-up gauge from low-power states (2) 500 µV step. Data Flash firmware default is 2 mV typical –1.5 –2.0 –2.5 mV
IWAKE Effective wake-up current threshold range Ideal RSNS = 1 mΩ –1000 –3000 mA
Ideal RSNS = 2 mΩ –500 –1500
Ideal RSNS = 5 mΩ –200 –600
VWAKE_ACC Wake-up detection accuracy (2) –250 250 µV
tWAKE I-WAKE detection delay options (1) Configurable with two delay options. Data Flash firmware default is 12 ms typical 9.6 12 14.4 ms
19.2 24 28.8
(1) Specified by design
(2) Data flash is configurable in FULL ACCESS mode and locked in SEALED. Accuracy is assured by factory trim at specified default threshold. A change in the factory threshold requires device calibration in the field.