SLUSAS3D April   2014  – June 2021 BQ28Z610

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current
    6. 7.6  Power Supply Control
    7. 7.7  Low-Voltage General Purpose I/O, TS1
    8. 7.8  Power-On Reset (POR)
    9. 7.9  Internal 1.8-V LDO
    10. 7.10 Current Wake Comparator
    11. 7.11 Coulomb Counter
    12. 7.12 ADC Digital Filter
    13. 7.13 ADC Multiplexer
    14. 7.14 Cell Balancing Support
    15. 7.15 Internal Temperature Sensor
    16. 7.16 NTC Thermistor Measurement Support
    17. 7.17 High-Frequency Oscillator
    18. 7.18 Low-Frequency Oscillator
    19. 7.19 Voltage Reference 1
    20. 7.20 Voltage Reference 2
    21. 7.21 Instruction Flash
    22. 7.22 Data Flash
    23. 7.23 Current Protection Thresholds
    24. 7.24 Current Protection Timing
    25. 7.25 N-CH FET Drive (CHG, DSG)
    26. 7.26 I2C Interface I/O
    27. 7.27 I2C Interface Timing
    28. 7.28 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Battery Parameter Measurements
        1. 8.3.1.1 BQ28Z610 Processor
      2. 8.3.2  Coulomb Counter (CC)
      3. 8.3.3  CC Digital Filter
      4. 8.3.4  ADC Multiplexer
      5. 8.3.5  Analog-to-Digital Converter (ADC)
      6. 8.3.6  ADC Digital Filter
      7. 8.3.7  Internal Temperature Sensor
      8. 8.3.8  External Temperature Sensor Support
      9. 8.3.9  Power Supply Control
      10. 8.3.10 Power-On Reset
      11. 8.3.11 Bus Communication Interface
      12. 8.3.12 Cell Balancing Support
      13. 8.3.13 N-Channel Protection FET Drive
      14. 8.3.14 Low Frequency Oscillator
      15. 8.3.15 High Frequency Oscillator
      16. 8.3.16 1.8-V Low Dropout Regulator
      17. 8.3.17 Internal Voltage References
      18. 8.3.18 Overcurrent in Discharge Protection
      19. 8.3.19 Short-Circuit Current in Charge Protection
      20. 8.3.20 Short-Circuit Current in Discharge 1 and 2 Protection
      21. 8.3.21 Primary Protection Features
      22. 8.3.22 Gas Gauging
      23. 8.3.23 Charge Control Features
      24. 8.3.24 Authentication
    4. 8.4 Device Functional Modes
      1. 8.4.1 Lifetime Logging Features
      2. 8.4.2 Configuration
        1. 8.4.2.1 Coulomb Counting
        2. 8.4.2.2 Cell Voltage Measurements
        3. 8.4.2.3 Current Measurements
        4. 8.4.2.4 Auto Calibration
        5. 8.4.2.5 Temperature Measurements
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements (Default)
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting Design Parameters
      3. 9.2.3 Calibration Process
      4. 9.2.4 Gauging Data Updates
        1. 9.2.4.1 Application Curve
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.20 Short-Circuit Current in Discharge 1 and 2 Protection

The short-circuit current in discharge (SCD) function detects catastrophic current conditions in the discharge direction. The short-circuit in discharge thresholds and delay times are configurable through the SCD1_CONTROL and SCD2_CONTROL registers. The thresholds and timing can be fine-tuned even further, based on a sense resistor with lower resistance or wider tolerance through the PROTECTION_CONTROL register. The detection circuit also incorporates a blanking delay before disabling the CHG and DSG FETs. When an SCD event occurs, the LATCH_STATUS[SCD1] or LATCH_STATUS[SCD2] bit is set to 1 and is latched until it is cleared and the fault condition has been removed.