SLUSET3 December   2022 BQ28Z620

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 BQ28Z620 Changes from BQ28Z610-R1
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Supply Current
    6. 8.6  Power Supply Control
    7. 8.7  Power-On Reset (POR)
    8. 8.8  Internal 1.8-V LDO
    9. 8.9  Current Wake Comparator
    10. 8.10 Coulomb Counter
    11. 8.11 ADC Digital Filter
    12. 8.12 ADC Multiplexer
    13. 8.13 Cell Balancing Support
    14. 8.14 Internal Temperature Sensor
    15. 8.15 NTC Thermistor Measurement Support
    16. 8.16 High-Frequency Oscillator
    17. 8.17 Low-Frequency Oscillator
    18. 8.18 Voltage Reference 1
    19. 8.19 Voltage Reference 2
    20. 8.20 Instruction Flash
    21. 8.21 Data Flash
    22. 8.22 Current Protection Thresholds
    23. 8.23 Current Protection Timing
    24. 8.24 N-CH FET Drive (CHG, DSG)
    25. 8.25 I2C Interface I/O
    26. 8.26 I2C Interface Timing
    27. 8.27 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Battery Parameter Measurements
        1. 9.3.1.1 BQ28Z620 Processor
      2. 9.3.2  Coulomb Counter (CC)
      3. 9.3.3  CC Digital Filter
      4. 9.3.4  ADC Multiplexer
      5. 9.3.5  Analog-to-Digital Converter (ADC)
      6. 9.3.6  ADC Digital Filter
      7. 9.3.7  Internal Temperature Sensor
      8. 9.3.8  External Temperature Sensor Support
      9. 9.3.9  Power Supply Control
      10. 9.3.10 Power-On Reset
      11. 9.3.11 Bus Communication Interface
      12. 9.3.12 I2C Timeout
      13. 9.3.13 Cell Balancing Support
      14. 9.3.14 N-Channel Protection FET Drive
      15. 9.3.15 Low Frequency Oscillator
      16. 9.3.16 High Frequency Oscillator
      17. 9.3.17 1.8-V Low Dropout Regulator
      18. 9.3.18 Internal Voltage References
      19. 9.3.19 Overcurrent in Discharge Protection
      20. 9.3.20 Short-Circuit Current in Charge Protection
      21. 9.3.21 Short-Circuit Current in Discharge 1 and 2 Protection
      22. 9.3.22 Primary Protection Features
      23. 9.3.23 Gas Gauging
      24. 9.3.24 Charge Control Features
      25. 9.3.25 Authentication
    4. 9.4 Device Functional Modes
      1. 9.4.1 Lifetime Logging Features
      2. 9.4.2 Configuration
        1. 9.4.2.1 Coulomb Counting
        2. 9.4.2.2 Cell Voltage Measurements
        3. 9.4.2.3 Current Measurements
        4. 9.4.2.4 Auto Calibration
        5. 9.4.2.5 Temperature Measurements
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements (Default)
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Setting Design Parameters
        2. 10.2.2.2 Calibration Process
        3. 10.2.2.3 Gauging Data Updates
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.11 Bus Communication Interface

The BQ28Z620 device has an I2C bus communication interface. This device has the option to broadcast information to a smart charger to provide key information to adjust the charging current and charging voltage based on the temperature or individual cell voltages.

CAUTION:

If the device is configured as a single-master architecture (an application processor) and an occasional NACK is detected in the operation, the master can resend the transaction. However, in a multi-master architecture, an incorrect ACK leading to accidental loss of bus arbitration can cause a master to wait incorrectly for another master to clear the bus. If this master does not get a bus-free signal, then it must have in place a method to look for the bus and assume it is free after some period of time. Also, if possible, set the clock speed to be 100 kHz or less to significantly reduce the issue described above for multi-mode operation.