SLUSBU5U November   2013  – October 2024 BQ2961 , BQ2962

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Details
        1. 7.3.1.1 Input Sense Voltage, Vx
        2. 7.3.1.2 Output Drive, OUT
        3. 7.3.1.3 Supply Input, VDD
        4. 7.3.1.4 Regulated Supply Output, REG
      2. 7.3.2 Overvoltage Sensing for OUT
      3. 7.3.3 Regulated Output Voltage and REG_EN Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1 NORMAL Mode
      2. 7.4.2 OVERVOLTAGE Mode
      3. 7.4.3 UNDERVOLTAGE Mode
      4. 7.4.4 CUSTOMER TEST MODE
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Typical values stated where TA = 25°C and VDD = 14.4 V, MIN/MAX values stated where TA = –40°C to +110°C, and VDD = 3 V to 15 V (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Voltage Protection Thresholds
VOVV(PROTECT) Overvoltage DetectionRIN = 1 kΩApplicable Voltage: 3.85 V to 4.6 V in 50-mV stepsV
VHYSOV Detection Hysteresis250300400mV
VOAOV Detection AccuracyTA = 25°C–1010mV
VOADRIFTOV Detection Accuracy Across TemperatureTA = –40°C–4040mV
TA = 0°C–2020mV
TA = 60°C–2424mV
TA = 110°C–5454mV
TA = 110°C–5454mV
Supply and Leakage Current
IDDSupply Current with REG on(Vn – Vn-1) = 2 V to 4.15 V, n = 1 to 4, VDD = top Vn voltage
(V1 – VSS) > VUVREG , IREG = 0 mA,		TA = 0°C to 60°C46µA
TA = –40°C to 110°C8µA
IDDSupply Current with REG off(Vn – Vn-1) = 2 V to 4.15 V, n = 1 to 4, VDD = top Vn voltage
(V1 – VSS) < VUVREG		TA = 0°C to 60°C12µA
TA = –40°C to 110°C4µA
IINInput Current at Vx Pins(Vn – Vn-1) = (V1 – VSS) = 3.8 V, VDD = top Vn voltage, TA = 25°C–0.10.1µA
Output Drive OUT, CMOS Active High
VOUTOutput Drive Voltage, Active High(Vn – Vn-1) or (V1 – VSS) > VOV, IOH = 100 µA, VDD = top Vn voltage678V
If three of four cells are short circuited, only one cell remains powered and > VOV, VDD = Vn (the remaining cell voltage), IOH = 100 µAVDD – 0.3V
(Vn – Vn-1) and (V1 – VSS) < VOV, VDD = sum of the cell stack voltage, IOL = 100 µA measured into OUT pin250400mV
IOUTHOUT Source Current (during OV)(Vn – Vn-1), (V3 – V2), or (V1 – VSS) > VOV, VDD = top Vn voltage,
forced OUT = 0 V, measured out of OUT pin		4.5mA
IOUTLOUT Sink Current (no OV)(Vn – Vn-1) and (V1 – VSS) < VOV, VDD = top Vn voltage, forced OUT = VDD, measured into OUT pin. Pull-up resistor RPU = 5 kΩ to VDD0.514mA
Internal Fixed Delay Timer
tDELAYOV Delay Time(1)Internal Fixed Delay, 3-s delay option2.433.6s
Internal Fixed Delay, 4-s delay option3.244.8s
Internal Fixed Delay, 5.5-s delay option4.45.56.6s
Internal Fixed Delay, 6.5-s delay option5.26.57.8s
tDELAY_CTMFault Detection Delay Time in Test Mode OV Delay TimeInternal Fixed Delay15ms
tDELAY_RESETOV delay timer count reset time; tDELAY resets when the cell voltage falls below VOV for tDELAY_RESET.(1)Internal Fixed Delay0.6ms
Regulated Supply Output, REG
VREGREG Supply at
500 µA load		VDD ≥ 4 V, IREG = 500 µA,
CREG = 0.47 µF		VREG = 3.3 V, 3.2343.3003.366V
VREG = 3.15 V, BQ29623.0873.1503.213
VREG = 3.0 V, BQ29622.9403.0003.060
VREG = 2.5 V, BQ29612.4502.5002.550
VREG = 1.8 V, BQ29611.7641.8001.836
VREGREG Supply from 0 to 2 mA loadVDD ≥ 4 V, IREG = 0 µA to 2 mA,
CREG = 0.47 µF		VREG = 3.3 V, BQ2961, BQ29623.2003.3003.400V
VREG = 3.15 V, BQ29623.0503.1503.250
VREG = 3.0 V, BQ29622.9003.0003.100
VREG = 2.5 V, BQ29612.4252.5002.575
VREG = 1.8 V, BQ29611.7461.8001.854
IREGREG Current OutputVDD ≥ 4 V, CREG = 0.47 µF02mA
IREG_ SC_LimitREG Output Short Circuit Current LimitREG = VSS, CREG = 0.47 µF4mA
RREG_ PDREG pull-down resistorREG is disabled.203045kΩ
Regulated Supply Output Enable, REG_EN
VIHHigh-level Input1.6V
VILLow-level Input0.4V
ILKGInput Leakage CurrentVIH < 6 V0.1µA
Regulated Supply Undervoltage Self-Disable
VUVREGUndervoltage detectionFactory Configuration: 2.0 V to 3.5 V in 50 mV steps, TA = 25°C–5050mV
VUVHYSUndervoltage Detection Hysteresis250300400mV
tUVDELAYUndervoltage Detection Delay4.567.5s
VUVQUALCell voltage to qualify for UV detection0.5V
(1) Specified by design. Not 100% tested in production.