SLUSF53 August   2024 BQ2969

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Details
        1. 7.3.1.1 Input Sense Voltage, Vx
        2. 7.3.1.2 Output Drive, OUT
        3. 7.3.1.3 Supply Input, VDD
        4. 7.3.1.4 Regulated Supply Output, REG
      2. 7.3.2 Overvoltage Sensing for OUT
      3. 7.3.3 Regulator Output Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 NORMAL Mode
      2. 7.4.2 OVERVOLTAGE Mode
      3. 7.4.3 UNDERVOLTAGE Mode
      4. 7.4.4 CUSTOMER TEST MODE
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

BQ2969 2-Series to 4-Series BQ2969 (Top View) Figure 5-1 2-Series to 4-Series BQ2969 (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME BQ2962
VDD 1 P Power supply input
V4 2 IA Sense input for positive voltage of the fourth cell from the bottom of the stack
V3 3 IA Sense input for positive voltage of the third cell from the bottom of the stack
V2 4 IA Sense input for positive voltage of the second cell from the bottom of the stack
V1 5 IA Sense input for positive voltage of the lowest cell from the bottom of the stack
VSS 6 P Electrically connected to integrated circuit ground and negative terminal of the lowest cell in the stack
OUT 7 OA Analog output drive for an overvoltage fault signal; CMOS output high or open-drain active pulldown or open-drain inactive pulldown
REG 8 OA Regulated supply output. Requires an external ceramic capacitor for stability
PWPD - P TI recommends connecting the exposed pad to VSS on PCB.
(1) IA = Analog input, OA = Analog Output, P = Power connection