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  • bq3050 CEDV Gas Gauge and Battery Pack Manager for 2-Series, 3-Series, and 4-Series Li-Ion Batteries

    • SLUSA92D January   2011  – May 2015

      PRODUCTION DATA.  

  • CONTENTS
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  • bq3050 CEDV Gas Gauge and Battery Pack Manager for 2-Series, 3-Series, and 4-Series Li-Ion Batteries
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current
    6. 7.6  Power-On Reset (POR)
    7. 7.7  WAKE FROM SLEEP
    8. 7.8  RBI RAM Backup
    9. 7.9  3.3-V Regulator
    10. 7.10 2.5-V Regulator
    11. 7.11 DISP, PRES, SMBD, SMBC
    12. 7.12 CHG, DSG FET Drive
    13. 7.13 Internal Precharge Limiting
    14. 7.14 GPOD
    15. 7.15 FUSE
    16. 7.16 LED5, LED4, LED3, LED2, LED1
    17. 7.17 Coulomb Counter
    18. 7.18 VC1, VC2, VC3, VC4
    19. 7.19 TS1, TS2
    20. 7.20 Internal Temperature Sensor
    21. 7.21 Internal Thermal Shutdown
    22. 7.22 High Frequency Oscillator
    23. 7.23 Low Frequency Oscillator
    24. 7.24 Internal Voltage Reference
    25. 7.25 Flash
    26. 7.26 OCD Current Protection
    27. 7.27 SCD1 Current Protection
    28. 7.28 SCD2 Current Protection
    29. 7.29 SCC Current Protection
    30. 7.30 SBS Timing Requirements
    31. 7.31 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Primary (1st Level) Safety Features
      2. 8.3.2 Secondary (2nd Level) Safety Features
      3. 8.3.3 Charge Control Features
      4. 8.3.4 Gas Gauging
      5. 8.3.5 Lifetime Data Logging Features
      6. 8.3.6 Authentication
    4. 8.4 Device Functional Modes
    5. 8.5 Configuration
      1. 8.5.1 Oscillator Function
      2. 8.5.2 System Present Operation
      3. 8.5.3 2-, 3-, or 4-Cell Configuration
      4. 8.5.4 Cell Balancing
        1. 8.5.4.1 Internal Cell Balancing
        2. 8.5.4.2 External Cell Balancing
    6. 8.6 Battery Parameter Measurements
      1. 8.6.1 Charge and Discharge Counting
      2. 8.6.2 Voltage
      3. 8.6.3 Current
      4. 8.6.4 Auto Calibration
      5. 8.6.5 Temperature
      6. 8.6.6 Communications
        1. 8.6.6.1 SMBus On and Off State
        2. 8.6.6.2 SBS Commands
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 High-Current Path
          1. 9.2.2.1.1 Protection FETs
          2. 9.2.2.1.2 Chemical Fuse
          3. 9.2.2.1.3 Lithium-Ion Cell Connections
          4. 9.2.2.1.4 Sense Resistor
          5. 9.2.2.1.5 ESD Mitigation
        2. 9.2.2.2 Gas Gauge Circuit
          1. 9.2.2.2.1 Differential Low-Pass Filter
          2. 9.2.2.2.2 Power Supply Decoupling and RBI
          3. 9.2.2.2.3 System Present
          4. 9.2.2.2.4 SMBus Communication
          5. 9.2.2.2.5 FUSE Circuitry
          6. 9.2.2.2.6 PFIN Detection
        3. 9.2.2.3 Secondary-Current Protection
          1. 9.2.2.3.1 Cell and Battery Inputs
          2. 9.2.2.3.2 External Cell Balancing
          3. 9.2.2.3.3 PACK and FET Control
          4. 9.2.2.3.4 Regulator Output
          5. 9.2.2.3.5 Temperature Output
          6. 9.2.2.3.6 LEDs
          7. 9.2.2.3.7 Safety PTC Thermistor
        4. 9.2.2.4 Secondary-Overvoltage Protection
          1. 9.2.2.4.1 Cell Inputs
          2. 9.2.2.4.2 Time-Delay Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DBT|38
    • MPDS368A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • slusa92d_oa
  • slusa92d_pm
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

bq3050 CEDV Gas Gauge and Battery Pack Manager for 2-Series, 3-Series, and 4-Series Li-Ion Batteries

1 Features

  • Fully Integrated 2-Series, 3-Series, and 4-Series Li-Ion or Li-Polymer Cell Battery Pack Manager and Protection
  • Advanced Compensated End-of-Discharge Voltage (CEDV) Gauging
  • High Side N-CH Protection FET Drive
  • Integrated Pre-Charge FET
  • Integrated Cell Balancing
  • Low Power Modes
    • Low Power: < 180 µA
    • Sleep < 76 µA
  • Full Array of Programmable Protection Features
    • Voltage
    • Current
    • Temperature
  • Sophisticated Charge Algorithms
    • JEITA
    • Enhanced Charging
    • Adaptive Charging
  • Supports Two-Wire SMBus v1.1 Interface
  • SHA-1 Authentication
  • Compact Package: 38-Lead TSSOP

2 Applications

  • Notebook/Netbook PCs
  • Medical and Test Equipment
  • Portable Instrumentation

3 Description

The Texas Instruments bq3050 Compensated End-of-Discharge Voltage (CEDV) Gas Gauge and Battery Pack Manager is a single-chip solution that provides a rich array of features for protection, authentication, and data gathering for 2-series, 3-series, and 4-series cell Li-Ion and Li-Polymer battery packs.

Using its integrated high-performance analog peripherals, the bq3050 device measures and maintains an accurate record of available capacity, voltage, current, temperature, and other critical parameters in Li-Ion or Li-Polymer batteries, and reports this information to the system host controller over an SMBus v1.1 compatible interface.

The bq3050 provides software-based 1st-level and 2nd-level safety protection for overvoltage, undervoltage, overtemperature, and overcharge conditions, as well as hardware-based protection for overcurrent in discharge and short circuit in charge and discharge conditions.

SHA-1 authentication with secure memory for authentication keys enables identification of genuine battery packs beyond any doubt.

The compact 38-lead TSSOP package minimizes solution cost and size for smart batteries while providing maximum functionality and safety for battery gauging applications.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
bq3050 TSSOP (38) 9.70 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

4 Simplified Schematic

bq3050 Diagram_3050.gif

5 Revision History

Changes from C Revision (December 2014) to D Revision

  • Added Community Resources sectionGo
  • Changed SRP, SRN absolute maximum values Go
  • Changed all occurrences of "bq29412" to "bq294705" Go

Changes from B Revision (October 2013) to C Revision

  • Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Deleted range from Storage temperature description Go

Changes from A Revision (June 2011) to B Revision

  • Changed TEST pin resistor valueGo

Changes from * Revision (January 2011) to A Revision

  • Changed TS2 pin numberGo
  • Changed Block DiagramGo
  • Changed schematicGo

6 Pin Configuration and Functions

bq3050 Pin_Out_bq3050.gif

Pin Functions

PIN NAME PIN NUMBER TYPE(1) DESCRIPTION
CHG 1 O Charge N-FET gate drive
PCR 2 O Internal Precharge FET output
BAT 3 P Alternate power source
VC1 4 I Sense input for positive voltage of top most cell in stack and cell balancing input for top most cell in stack
VC2 5 I Sense input for positive voltage of third lowest cell in stack and cell balancing input for third lowest cell in stack
VC3 6 I Sense input for positive voltage of second lowest cell in stack and cell balancing input for second lowest cell in stack
VC4 7 I Sense input for positive voltage of lowest cell in stack and cell balancing input for lowest cell in stack
VSS 8 P Device ground
VSS 9 P Device ground
TS1 10 AI Temperature sensor 1 thermistor input
SRP 11 AI Differential Coulomb Counter input
NC 12 — Not internally connected. Connect to VSS.
SRN 13 AI Differential Coulomb Counter input
NC 14 — Not internally connected. Connect to VSS.
TS2 15 AI Temperature sensor 2 thermistor input
PRES 16 I Host system present input
SMBD 17 I/OD SMBus v1.1 data line
NC 18 — Not internally connected. Connect to VSS.
SMBC 19 I/OD SMBus v1.1 clock line
DISP 20 I Display active input
NC 21 — Not internally connected. Connect to VSS.
LED5 22 O LED display constant current sink
LED4 23 O LED display constant current sink
LED3 24 O LED display constant current sink
LED2 25 O LED display constant current sink
LED1 26 O LED display constant current sink
RBI 27 P RAM backup
REG25 28 P 2.5-V regulator output
VSS 29 P Device ground
VSS 30 P Device ground
REG33 31 P 3.3-V regulator output
TEST 32 — Test pin, connect to VSS through 10-kΩ resistor
FUSE 33 O Fuse drive
PCHGIN 34 I Internal Precharge FET input
VCC 35 P Power supply voltage
GPOD 36 I/OD High voltage general purpose I/O
PACK 37 P Alternate power source
DSG 38 O Discharge N-FET gate drive
(1) P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range, VMAX VCC, PCHGIN, PCR, TEST, PACK w.r.t. VSS –0.3 34 V
Input voltage range, VIN VC1, BAT VVC2 – 0.3 VVC2 + 8.5 V
or 34 V,
whichever is lower		 V
VC2 VVC3 – 0.3 VVC3 + 8.5 V
VC3 VVC4 – 0.3 VVC4 + 8.5 V
VC4 VSRP – 0.3 VSRP + 8.5 V
SRP, SRN –0.5 0.5
LED1, LED2, LED3, LED4, LED5, SMBC, SMBD VSS – 0.3 6.0
DISP,TS1, TS2, PRES –0.3 V VREG25 + 0.3 V
Output voltage range, VO DSG –0.3 VPACK + 20 V or
VSS + 34 V, whichever is lower		 V
CHG –0.3 VBAT + 20 V or
VSS + 34 V, whichever is lower
GPOD, FUSE –0.3 34
RBI, REG25 –0.3 2.75
REG33 –0.3 5.0
Maximum VSS current, ISS 50 mA
Current for cell balancing, ICB 10
ESD Rating HBM, VCx Only 1 kV
Functional Temperature, TFUNC –40 110 °C
Storage temperature, TSTG –65 150 °C
Lead temperature (soldering, 10 s), TSOLDER 300 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage VCC, PACK, PCHGIN, PCR 25 V
BAT 3.8 VVC2 + 5.0
VSTARTUP Start up voltage at PACK 3.0 5.5 V
VIN Input voltage range VC1, BAT VVC2 VVC2 + 5.0 V
VC2 VVC3 VVC3 + 5.0
VC3 VVC4 VVC4 + 5.0
VC4 VSRP VSRP + 5.0
VCn – VC(n+1), (n=1, 2, 3, 4) 0 5.0
PACK 25
SRP to SRN –0.2 0.2
CREG33 External 3.3V REG capacitor 1 µF
CREG25 External 2.5V REG capacitor 1 µF
TOPR Operating temperature –40 85 °C

7.4 Thermal Information

THERMAL METRIC bq3050 UNIT
TSSOP (DBT)
38 PINS
RθJA Junction-to-ambient thermal resistance 64.2 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 16.5
RθJB Junction-to-board thermal resistance 31.2
ψJT Junction-to-top characterization parameter 0.3
ψJB Junction-to-board characterization parameter 26.9
RθJC(bot) Junction-to-case(bottom) thermal resistance n/a

7.5 Supply Current

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Normal CHG on, DSG on, no Flash write 410 µA
Sleep CHG on, DSG on, no SBS communication 160
CHG off, DSG off, no SBS communication 80
Shutdown 3.7

7.6 Power-On Reset (POR)

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT– Negative-going voltage input At REG25 1.9 2.0 2.1 V
VHYS POR Hysteresis At REG25 65 125 165 mV

7.7 WAKE FROM SLEEP

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VWAKE VWAKE Threshold VWAKE 0.2 1.2 2.0 mV
VWAKE 0.4 2.4 3.6
VWAKE 2.0 5.0 6.8
VWAKE 5.3 10 13
VWAKE_TCO Temperature drift of VWAKE accuracy 0.5% °C
tWAKE Time from application of current and wake of bq3050 0.2 1 ms

7.8 RBI RAM Backup

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(RBI) RBI data-retention input current VRBI > V(RBI)MIN, VCC < VIT 20 1100 nA
VRBI > V(RBI)MIN, VCC < VIT,
TA= 0°C to 70°C		 500
V(RBI) RBI data-retention voltage 1 V

7.9 3.3-V Regulator

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREG33 Regulator output voltage 3.8 V < VCC or BAT ≤ 5 V,
ICC ≤4 mA		 2.4 3.5 V
5V < VCC or BAT ≤ 6.8 V,
ICC ≤13 mA		 3.1 3.3 3.5
6.8 V < VCC or BAT ≤ 20 V,
ICC ≤ 30 mA		 3.1 3.3 3.5
IREG33 Regulator output current 2 mA
ΔV(VDDTEMP) Regulator output change with temperature VCC or BAT = 14.4 V, IREG33 = 2 mA 0.2%
ΔV(VDDLINE) Line regulation VCC or BAT = 14.4 V, IREG33 = 2 mA 1 13 mV
ΔV(VDDLOAD) Load regulation VCC or BAT = 14.4 V, IREG33 = 2 mA 5 18 mV
I(REG33MAX) Current limit VCC or BAT = 14.4 V, VREG33 = 3 V 70 mA
VCC or BAT = 14.4 V, VREG33 = 0 V 33

7.10 2.5-V Regulator

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREG25 Regulator output voltage IREG25 = 10 mA 2.35 2.5 2.55 V
IREG25 Regulator Output Current 3 mA
ΔV(VDDTEMP) Regulator output change with temperature VCC or BAT = 14.4 V, IREG25 = 2 mA 0.25%
ΔV(VDDLINE) Line regulation VCC or BAT = 14.4 V, IREG25 = 2 mA 1 4 mV
ΔV(VDDLOAD) Load regulation VCC or BAT = 14.4 V, IREG25 = 2 mA 20 40 mV
I(REG33MAX) Current limit VCC or BAT = 14.4 V, VREG25 = 2.3 V 65 mA
VCC or BAT = 14.4 V, VREG25 = 0 V 23

7.11 DISP, PRES, SMBD, SMBC

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input DISP, PRES, SMBD, SMBC 2.0 V
VIL Low-level input DISP, PRES, SMBD, SMBC 0.8 V
VOL Low-level output voltage SMBD, SMBC 0.4 V
CIN Input capacitance DISP, PRES, SMBD, SMBC 5 pF
ILKG Input leakage current DISP, PRES, SMBD, SMBC 1 μA
IWPU Weak Pull Up Current PRES, VOH = VREG25 – 0.5 V 60 120 μA
I(DISP) DISP source currents DISP active, DISP = VREG25 – 0.6 V –3 mA
ILKG(DISP) DISP leakage current DISP inactive –0.22 0.22 μA
RPD(SMBx) SMBC, SMBD Pull-Down TA = –40 to 100˚C 550 775 1000 kΩ

7.12 CHG, DSG FET Drive

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(FETON) Output voltage, charge, and discharge FETs on VO(FETONDSG) = V(DSG) – VPACK, VGS connect 10 MΩ, VCC 3.8 V to 8.4 V 8.0 9.7 12 V
VO(FETONDSG) = V(DSG) – VPACK, VGS connect 10 MΩ, VCC > 8.4 V 9.0 11 12
VO(FETONCHG) = V(CHG) – VBAT, VGS connect 10 MΩ, VCC 3.8 V to 8.4 V 8.0 9.7 12
VO(FETONCHG) = V(CHG) – VBAT, VGS connect 10 MΩ, VCC > 8.4 V 9.0 11 12
V(FETOFF) Output voltage, charge and discharge FETs off VO(FETOFFDSG) = V(DSG) – VPACK –0.4 0.4 V
VO(FETOFFCHG) = V(CHG) – VBAT –0.4 0.4
tr Rise time CL= 4700 pF
RG= 5.1 kΩ
VCC < 8.4
VDSG: VBAT to VBAT + 4 V
VCHG: VPACK to VPACK + 4 V		 800 1400 μs
CL = 4700 pF
RG = 5.1 kΩ
VCC > 8.4
VDSG: VBAT to VBAT + 4 V
VCHG: VPACK to VPACK + 4 V		 200 500
tf Fall time CL = 4700 pF
RG = 5.1 kΩ
VDSG: VBAT + VO(FETONDSG) to VBAT + 1 V
VCHG: VPACK + VO(FETONCHG) to VPACK + 1 V		 80 200 μs

7.13 Internal Precharge Limiting

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IPCHGMAX Maximum Precharge current 3-cell and 4-cell configuration 100 mA
RPCHG_RDSON Internal Precharge FET RDSON VDS(PRECHG) ≥ 1 V, VCC < 8.4 V 30 55 85 Ω
VDS(PRECHG) ≥ 1 V, VCC ≥ 8.4 V 15 30 55

7.14 GPOD

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VPU_GPOD GPOD Pull-Up Voltage VCC V
VOL_GPOD GPOD Output Voltage Low IOL = 1 mA 0.3 V

7.15 FUSE

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH(FUSE) High Level FUSE Output VCC = 3.8 V to 9 V 2.4 8.5 V
VCC = 9 V to 25 V 7 8 9
VIH(FUSE) Weak pull-up current in off state(1) 2.8 V
100 nA
tR(FUSE) FUSE Output Rise Time CL = 1 nF, VCC = 9 V to 25 V, VOH(FUSE) = 0 V to 5 V 5 20 μs
ZO(FUSE) FUSE Output Impedance 2 5 kΩ
(1) Verified by design. Not production tested.

7.16 LED5, LED4, LED3, LED2, LED1

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CIN Input capacitance 5 pF
ILKG Input leakage current 1 μA
IOL Low-level output current VOL = 0.4 V,
3 mA setting		 2.5 3.5 4.5 mA
VOL = 0.4 V,
4 mA setting		 3.0 4.5 6.0
VOL = 0.4 V,
5 mA setting		 3.5 5.5 7.5
ILEDx Current matching between LEDx 0.1 mA

7.17 Coulomb Counter

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range SRP – SRN –0.20 0.25 V
Conversion time Single conversion 250 ms
Resolution (no missing codes) 16 Bits
Effective resolution Single conversion, signed 15 Bits
Offset error Post calibrated 10 µV
Offset error drift 0.3 0.5 µV/°C
Full-scale error –0.8% 0.2% 0.8%
Full-scale error drift 150 PPM/°C
Effective input resistance 2.5 mΩ

7.18 VC1, VC2, VC3, VC4

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range VC4 – VC3, VC3 – VC2, VC2 – VC1, VC1 – VSS –0.20 8 V
Conversion time Single conversion 32 ms
Resolution (no missing codes) 16 Bits
Effective resolution Single conversion, signed 15 Bits
R(BAL) RDS(ON) for internal FET at VDS > 2 V VDS = VC4 – VC3, VC3 – VC2,
VC2 – VC1, VC1 – VSS		 200 310 430 Ω
RDS(ON) for internal FET at VDS > 4 V VDS = VC4 – VC3, VC3 – VC2,
VC2 – VC1, VC1 – VSS		 60 125 230

7.19 TS1, TS2

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R Internal Pull Up Resistor 16.5 17.5 19.0 KΩ
RDRIFT Internal Pull Up Resistor Drift From 25°C 200 PPM/°C
RPAD Internal Pin Pad resistance 84 Ω
VIN Input voltage range TS1 – VSS, TS2 – VSS –0.20 0.8 × VREG25 V
Conversion Time 16 ms
Resolution (no missing codes) 16 Bits
Effective resolution 11 12 Bits

7.20 Internal Temperature Sensor

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(TEMP) Temperature sensor voltage –1.9 –2.0 –2.1 mV/°C
Conversion Time 16 ms
Resolution (no missing codes) 16 Bits
Effective resolution 11 12 Bits

7.21 Internal Thermal Shutdown

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TMAX1 Maximum PCHG temperature 110 150 °C
TMAX2 Maximum REG33 temperature 125 175 °C
TRECOVER Recovery hysteresis temperature 10 °C
tPROTECT Protection time 5 µs

7.22 High Frequency Oscillator

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(OSC) Operating frequency of CPU Clock 4.194 MHz
f(EIO) Frequency error(1)(2) TA = –20°C to 70°C –2% ±0.25% 2%
TA = –40°C to 85°C –3% ±0.25% 3%
t(SXO) Start-up time(3) TA = –25°C to 85°C 3 6 ms
(1) The frequency error is measured from 4.194 MHz.
(2) The frequency drift is included and measured from the trimmed frequency at VREG25 = 2.5 V, TA = 25°C.
(3) The startup time is defined as the time it takes for the oscillator output frequency to be ±3% when the device is already powered.

7.23 Low Frequency Oscillator

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(LOSC) Operating frequency 32.768 kHz
f(LEIO) Frequency error(1)(3) TA = –20°C to 70°C –1.5% ±0.25% 1.5%
TA = –40°C to 85°C –2.5% ±0.25% 2.5%
t(LSXO) Start-up time(2) TA = –25°C to 85°C 100 μs
(1) The frequency drift is included and measured from the trimmed frequency at VCC = 2.5 V, TA = 25°C.
(2) The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
(3) The frequency error is measured from 32.768 kHz.

7.24 Internal Voltage Reference

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF Internal Reference Voltage 1.215 1.225 1.230 V
VREF_DRIFT Internal Reference Voltage Drift TA = –25°C to 85°C ±80 PPM/°C
TA = 0°C to 60°C ±50

7.25 Flash

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT
Data retention 10 Year
Flash programming write-cycles Data Flash 20k Cycle
Instruction Flash 1k
ICC(PROG_DF) Data Flash-write supply current TA = –40°C to 85°C 3 4 mA
ICC(ERASE_DF) Data Flash-erase supply current TA = –40°C to 85°C 3 18 mA
(1) Verified by design. Not production tested.

7.26 OCD Current Protection

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(OCD) OCD detection threshold voltage range, typical RSNS = 0 50 200 mV
RSNS = 1 25 100
ΔV(OCDT) OCD detection threshold voltage program step RSNS = 0 10 mV
RSNS = 1 5
V(OFFSET) OCD offset –10 10 mV
V(Scale_Err) OCD scale error –10% 10%
t(OCDD) Over Current in Discharge Delay 1 31 ms
t(OCDD_STEP) OCDD Step options 2 ms
t(DETECT) Current fault detect time VSRP – SRN = VTHRESH + 12.5 mV 160 µs
tACC Over Current and Short Circuit delay time accuracy Accuracy of typical delay time –20% 20%

7.27 SCD1 Current Protection

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(SDC1) SCD1 detection threshold voltage range, typical RSNS = 0 100 450 mV
RSNS = 1 50 225
ΔV(SCD1T) SCD1 detection threshold voltage program step RSNS = 0 50 mV
RSNS = 1 25
V(OFFSET) SCD1 offset –10 10 mV
V(Scale_Err) SCD1 scale error –10% 10%
t(SCD1D) Short Circuit in Discharge Delay AFE.STATE_CNTL[SCDDx2] = 0 0 915 µs
AFE.STATE_CNTL[SCDDx2] = 1 0 1830
t(SCD1D_STEP) SCD1D Step options AFE.STATE_CNTL[SCDDx2] = 0 61 µs
AFE.STATE_CNTL[SCDDx2] = 1 122
t(DETECT) Current fault detect time VSRP – SRN = VTHRESH + 12.5 mV 160 µs
tACC Over Current and Short Circuit delay time accuracy Accuracy of typical delay time –20% 20%

7.28 SCD2 Current Protection

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(SDC2) SCD2 detection threshold voltage range, typical RSNS = 0 100 450 mV
RSNS = 1 50 225
ΔV(SCD2T) SCD2 detection threshold voltage program step RSNS = 0 50 mV
RSNS = 1 25
V(OFFSET) SCD2 offset –10 10 mV
V(Scale_Err) SCD2 scale error –10% 10%
t(SCD1D) Short Circuit in Discharge Delay AFE.STATE_CNTL[SCDDx2] = 0 0 458 µs
AFE.STATE_CNTL[SCDDx2] = 1 0 915
t(SCD2D_STEP) SCD2D Step options AFE.STATE_CNTL[SCDDx2] = 0 30.5 µs
AFE.STATE_CNTL[SCDDx2] = 1 61
t(DETECT) Current fault detect time VSRP – SRN = VTHRESH + 12.5 mV 160 µs
tACC Over Current and Short Circuit delay time accuracy Accuracy of typical delay time –20% 20%

7.29 SCC Current Protection

Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(SCCT) SCC detection threshold voltage range, typical RSNS = 0 –100 –300 mV
RSNS = 1 –50 –225
ΔV(SCCDT) SCC detection threshold voltage program step RSNS = 0 –50 mV
RSNS = 1 –25
V(OFFSET) SCC offset –10 10 mV
V(Scale_Err) SCC scale error –10% 10%
t(SCCD) Short Circuit in Charge Delay 0 915 ms
t(SCCD_STEP) SCCD Step options 61 ms
t(DETECT) Current fault detect time VSRP – SRN = VTHRESH + 12.5 mV 160 µs
tACC Over Current and Short Circuit delay time accuracy Accuracy of typical delay time –20% 20%

7.30 SBS Timing Requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSMB SMBus operating frequency Slave mode, SMBC 50% duty cycle 10 100 kHz
fMAS SMBus master clock frequency Master mode, no clock low slave extend 51.2 kHz
tBUF Bus free time between start and stop 4.7 µs
tHD:STA Hold time after (repeated) start 4.0 µs
tSU:STA Repeated start setup time 4.7 µs
tSU:STO Stop setup time 4.0 µs
tHD:DAT Data hold time 300 ns
tSU:DAT Data setup time 250 ns
tTIMEOUT Error signal/detect See(1) 25 35 ms
tLOW Clock low period 4.7 µs
tHIGH Clock high period See(2) Disabled
tHIGH Clock high period See(2) 4.0 50 µs
tLOW:SEXT Cumulative clock low slave extend time See(3) 25 ms
tLOW:MEXT Cumulative clock low master extend time See(4) 10 ms
tF Clock/data fall time See(5) 300 ns
tR Clock/data rise time See(6) 1000 ns
(1) The bq3050 times out when any clock low exceeds tTIMEOUT.
(2) tHIGH, Max, is the minimum bus idle time. SMBC = 1 for t > 50 µs causes reset of any transaction involving bq3050 that is in progress. This specification is valid when the THIGH_VAL=0. If THIGH_VAL = 1, then the value of THIGH is set by THIGH_1,2 and the timeout is not SMBus standard.
(3) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time tR = VILMAX – 0.15) to (VIHMIN + 0.15)
(6) Fall time tF = 0.9 VDD to (VILMAX – 0.15)
bq3050 SMBusTiming.gifFigure 1. SMBus Timing Diagram

7.31 Typical Characteristics

bq3050 C004_SLUSA92.png
Figure 2. CC Input Offset Drift Overtemperature
bq3050 C005_SLUSA92.png
Figure 3. ADC Input Offset Drift Overtemperature

8 Detailed Description

8.1 Overview

The bq3050 measures the voltage, temperature, and current to determine battery capacity and state-of-charge (SOC). The bq3050 monitors charge and discharge activity by sensing the voltage across a small value resistor (5 mΩ to 20 mΩ, typical) between the SRP and SRN pins and in series with the battery. By integrating charge passing through the battery, the battery’s SOC is adjusted during battery charge or discharge. Measurements of OCV and charge integration determine chemical SOC.

The Qmax values are taken from a cell manufacturers' data sheet multiplied by the number of parallel cells, and is also used for the value in Design Capacity. It uses the OCV and Qmax value to determine StateOfCharge() on battery insertion, device reset, or on command. The FullChargeCapacity() is reported as the learned capacity available from full charge until Voltage() reaches the EDV0 threshold. As Voltage() falls below the Shutdown Voltage for Shutdown Time and has been out of SHUTDOWN mode for at least Shutdown Time, the PF Flags1 () [VSHUT] bit is set. For additional details, see bq3050 Technical Reference Manual (SLUU485).

Fuel gauging is derived from the Compensated End of Discharge Voltage (CEDV) method, which uses a mathematical model to correlate remaining state of charge (RSOC) and voltage near to the end of discharge state. This requires a full-discharge cycle for a single-point FCC update. The implementation models cell voltage (OCV) as a function of battery SOC, temperature, and current. The impedance is also a function of SOC and temperature, which can be satisfied by using seven parameters: EMF, C0, R0, T0, R1, TC, and C1.

8.2 Functional Block Diagram

bq3050 FunctionBD_3050.gif

8.3 Feature Description

8.3.1 Primary (1st Level) Safety Features

The bq3050 supports a wide range of battery and system protection features that can easily be configured. The primary safety features include:

  • Cell Overvoltage/Undervoltage Protection
  • Charge and Discharge Overcurrent
  • Short-Circuit
  • Charge and Discharge Over-Temperature
  • AFE Watchdog

8.3.2 Secondary (2nd Level) Safety Features

The secondary safety features of the bq3050 can be used to indicate more serious faults via the FUSE pin. This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or discharging. The secondary safety protection features include:

  • Safety Overvoltage
  • Safety Overcurrent in Charge and Discharge
  • Safety Overtemperature in Charge and Discharge
  • Charge FET, Discharge FET, and Precharge FET Faults
  • Cell Imbalance Detection
  • Fuse Blow by Secondary Voltage Protection IC
  • AFE Register Integrity Fault (AFE_P)
  • AFE Communication Fault (AFE_C)

8.3.3 Charge Control Features

The bq3050 charge control features include:

  • Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active temperature range
  • Handles more complex charging profiles. Allows for splitting the standard temperature range into two sub-ranges and allows for varying the charging current according to the cell voltage
  • Reports the appropriate charging current needed for constant current charging and the appropriate charging voltage needed for constant voltage charging to a smart charger using SMBus broadcasts
  • Reduce the charge difference of the battery cells in fully charged state of the battery pack gradually using a voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for cell balancing to be active. This prevents fully charged cells from overcharging and causing excessive degradation and also increases the usable pack energy by preventing premature charge termination.
  • Supports pre-charging/zero-volt charging
  • Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range
  • Reports charging fault and also indicate charge status via charge and discharge alarms

8.3.4 Gas Gauging

The bq3050 uses the CEDV algorithm to measure and calculate the available capacity in battery cells. The bq3050 accumulates a measure of charge and discharge currents and compensates the charge current measurement for the temperature and state-of-charge of the battery. The bq3050 estimates self-discharge of the battery and also adjusts the self-discharge estimation based on temperature. See the bq3050 Technical Reference Manual (SLUU485) for further details.

8.3.5 Lifetime Data Logging Features

The bq3050 offers limited lifetime data logging for the following critical battery parameters:

  • Lifetime Maximum Temperature
  • Lifetime Minimum Temperature
  • Lifetime Maximum Battery Cell Voltage
  • Lifetime Minimum Battery Cell Voltage

8.3.6 Authentication

  • The bq3050 supports authentication by the host using SHA-1.
  • SHA-1 authentication by the gas gauge is required for unsealing and full access.

8.4 Device Functional Modes

The bq3050 supports three power modes to reduce power consumption:

  • In NORMAL Mode, the bq3050 performs measurements, calculations, protection decisions, and data updates in 0.25-s intervals. Between these intervals, the bq3050 is in a reduced power stage.
  • In SLEEP Mode, the bq3050 performs measurements, calculations, protection decisions, and data updates in adjustable time intervals. Between these intervals, the bq3050 is in a reduced power stage. The bq3050 has a wake function that enables exit from Sleep mode when current flow or failure is detected.
  • In SHUTDOWN Mode, the bq3050 is completely disabled.

8.5 Configuration

8.5.1 Oscillator Function

The bq3050 fully integrates the system oscillators and does not require any external components to support this feature.

8.5.2 System Present Operation

The bq3050 checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external system, the bq3050 detects this as system present.

8.5.3 2-, 3-, or 4-Cell Configuration

In a 2-cell configuration, VC1 is shorted to VC2 and VC3. In a 3-cell configuration, VC1 is shorted to VC2.

8.5.4 Cell Balancing

The device supports cell balancing by bypassing the current of each cell during charging or at rest. If the device's internal bypass is used, up to 10 mA can be bypassed and multiple cells can be bypassed at the same time. Higher cell balance current can be achieved by using an external cell balancing circuit. In external cell balancing mode, only one cell at a time can be balanced.

The cell balancing algorithm determines the amount of charge needed to be bypassed to balance the capacity of all cells.

8.5.4.1 Internal Cell Balancing

When internal cell balancing is configured, the cell balance current is defined by the external resistor RVC at the VCx input. See Figure 4.

bq3050 int_cell_lus996.gifFigure 4. Internal Cell Balancing with RVC

8.5.4.2 External Cell Balancing

When external cell balancing is configured, the cell balance current is defined by RB. See Figure 5. Only one cell at a time can be balanced.

bq3050 ext_cell_lus996.gifFigure 5. External Cell Balancing with RB

8.6 Battery Parameter Measurements

8.6.1 Charge and Discharge Counting

The bq3050 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a second delta-sigma ADC for individual cell and battery voltage and temperature measurement.

The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage drop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolar signals from –0.25 V to 0.25 V. The bq3050 detects charge activity when VSR = V(SRP) – V(SRN) is positive, and discharge activity when VSR = V(SRP) – V(SRN) is negative. The bq3050 continuously integrates the signal over time, using an internal counter. The fundamental rate of the counter is 0.65 nVh.

8.6.2 Voltage

The bq3050 updates the individual series cell voltages at 0.25-second intervals. The internal ADC of the bq3050 measures the voltage, and scales and calibrates it appropriately. This data is also used to calculate the impedance of the cell for the CEDV gas-gauging.

8.6.3 Current

The bq3050 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current using a 5-mΩ to 20-mΩ typ. sense resistor.

8.6.4 Auto Calibration

The bq3050 provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for maximum charge measurement accuracy. The bq3050 performs auto-calibration when the SMBus lines stay low continuously for a minimum of 5 s.

8.6.5 Temperature

The bq3050 has an internal temperature sensor and inputs for two external temperature sensors. All three temperature sensor options are individually enabled and configured for cell or FET temperature. Two configurable thermistor models are provided to allow the monitoring of cell temperature in addition to FET temperature, which may be of a higher temperature type.

8.6.6 Communications

The bq3050 uses SMBus v1.1 with Master Mode and packet error checking (PEC) options per the SBS specification.

8.6.6.1 SMBus On and Off State

The bq3050 detects an SMBus off state when SMBC and SMBD are low for two or more seconds. Clearing this state requires that either SMBC or SMBD transition high. The communication bus will resume activity within 1 ms.

8.6.6.2 SBS Commands

See the bq3050 Technical Reference Manual(SLUU485) for further details.

 
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