SLUS987C January 2011 – December 2019 BQ33100
PRODUCTION DATA.
Capacitor voltage balancing in the BQ33100 is accomplished by connecting an external parallel bypass load to each capacitor, and enabling the bypass load depending on each individual capacitors voltage level. The bypass load is typically formed by a P-CH MOSFET and a resistor connected in series across each capacitor. The filter resistors that connect the capacitor tabs to VC1 to approximately VC4 pins of the BQ33100 are required to be 1 k ohms to support this function on all capacitors other than the lowest. The lowest capacitor bypass is enabled through the VC5BAL pin. Capacitor Voltage Balancing is only operational after the ManufacturerAccess Lifetime and Capacitor Balancing Enable (0x21) command is sent to the BQ33100.
Using this circuit, the BQ33100 balances the capacitors during charge and after charge termination by discharging those capacitors with voltage above the threshold set in CB Threshold and if the ΔV in capacitor voltages exceeds the value programmed in CB Min. During capacitor voltage balancing, the BQ33100 measures the capacitor voltages periodically (during which time the voltage balancing circuit is turned off) and based on the capacitor voltages, the BQ33100 selects the appropriate capacitor to discharge. When ΔV of CapacitorVoltage5...1 < CB Min then capacitor voltage balancing stops. Capacitor voltage balancing restarts when ΔV of CapacitorVoltage5...1 ≥ CB Restart to avoid balancing start-stop oscillations.
Capacitor voltage balancing only occurs when:
Capacitor voltage balancing stops when:
This feature is disabled when in STACK mode, when Operation Cfg[STACK ] = 1.