The bq34110 CEDV Battery Gas Gauge provides CEDV gas gauging and End-Of-Service (EOS) Determination for single- and multi-cell batteries. The device includes enhanced features to support applications where the battery is kept fully charged and is rarely discharged, such as found in a wide variety of backup systems. The bq34110 gas gauge supports multiple battery chemistries, including Li-Ion and LiFePO4, lead acid (PbA), Nickel Metal Hydride (NiMH), and Nickel Cadmium (NiCd).
The gas gauging function uses voltage, current, and temperature data with Compensated End-of-Discharge Voltage (CEDV) technology to provide State-Of-Charge (SOC) and State-Of-Health (SOH) data. The gas gauge also incorporates an End-Of-Service (EOS) Determination function that alerts when battery capability has degraded and is approaching the conclusion of its usable service.
The data available from the gauge can be read by the host through a 400-kHz I2C bus. Two ALERT outputs are also available to interrupt the host or can be used for other functions, based on a variety of configurable options.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
bq34110 | TSSOP (14) | 5.00 mm × 4.40 mm |
DATE | REVISION | NOTES |
---|---|---|
November 2016 | B | PRODUCT PREVIEW to Production Data |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
VEN/GPIO | 1 | O(1) | Active High Voltage Translation Enable. This signal is used optionally to switch the input voltage divider on/off to reduce the power consumption (typ 45 μA) of the divider network. It can also be used as a general purpose output. |
ALERT1 | 2 | O | Open drain output for use as system alert or charger control. Pull-up voltage limited |
LEN | 3 | O | Push-pull external voltage divider control output |
BAT | 4 | P | Voltage measurement input |
CE | 5 | I | Chip enable. Internal LDO is powered down when driven low. |
REGIN | 6 | P | Internal integrated LDO input. Decouple with 0.1-µF ceramic capacitor to VSS. |
REG25 | 7 | P | 2.5-V output voltage of the internal integrated LDO. Decouple with 1-µF ceramic capacitor to VSS. |
VSS | 8 | P | Device ground |
SRP | 9 | I | Analog input pin connected to the internal coulomb-counter peripheral for integrating a small voltage between SRP and SRN, where SRP is nearest the BAT– connection. |
SRN | 10 | I | Analog input pin connected to the internal coulomb-counter peripheral for integrating a small voltage between SRP and SRN, where SRN is nearest the PACK– connection. |
TS | 11 | I | Pack thermistor voltage sense (use 103AT-type thermistor) |
ALERT2 | 12 | O | Open drain output for use as system alert or charger control |
SCL | 13 | I | Open drain slave I2C serial communication clock input. Use with an external 10-kΩ pull-up resistor (typical). |
SDA | 14 | I/O | Open drain slave I2C serial communication data line. Use with an external 10-kΩ pull-up resistor (typical). |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VREGIN | Regulator input range | –0.3 | 5.5 | V |
VCE | CE input pin | –0.3 | VREGIN + 0.3 | V |
VREG25 | Supply voltage range | –0.3 | 2.75 | V |
VIOD | Open-drain I/O pins (SDA, SCL, ALERT2) | –0.3 | 5.5 | V |
VBAT | BAT input pin | –0.3 | 5.5 | V |
VI | Input voltage range to all other pins (SRP, SRN, TS, ALERT1, VEN/GPIO, LEN) | –0.3 | VREG25 + 0.3 | V |
TA | Operating free-air temperature range | –40 | 85 | °C |
TJ | Operating junction temperature range | –40 | 100 | °C |
TF | Functional temperature range | –40 | 100 | °C |
TSTG | Storage temperature range | –65 | 150 | °C |
Lead temperature (soldering, 10 s) | –40 | 100 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, BAT pin(1) | ±1500 | V |
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all other pins(1) | ±2000 | |||
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
THERMAL METRIC(1) | bq34110 | UNIT | |
---|---|---|---|
TSSOP (PW) | |||
14 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 103.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 31.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 46.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 2.0 | °C/W |
ψJB | Junction-to-board characterization parameter | 45.9 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ICC_NORMAL | Normal operating current | Device in NORMAL mode, ILOAD > Sleep Current | 133 | µA | ||
ISNOOZE(1) | Sleep+ operation mode current | Device in SNOOZE mode, ILOAD < Sleep Current | 53 | µA | ||
ISLEEP(1) | Low-power SLEEP mode current | Device in SLEEP mode, ILOAD < Sleep Current | 22 | µA | ||
ISHUTDOWN | SHUTDOWN mode current | Fuel gauge in SHUTDOWN mode, CE pin < VIL(CE) max | 0.01 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIT+ | Positive-going battery voltage input at REGIN | 2.20 | V | |||
VHYS | Power-on reset hysteresis | 115 | mV |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VREG25 | Regulator output voltage | 2.7 V ≤ VREGIN ≤ 4.5 V, IOUT ≤ 16 mA TA = –40°C to 85°C |
2.3 | 2.5 | 2.7 | V |
2.45 V ≤ VREGIN < 2.7 V, IOUT ≤ 3 mA TA = –40°C to 85°C |
2.3 | |||||
ISHORT(2) | Short circuit current limit | VREG25 = 0 V TA = –40°C to 85°C |
250 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
GTEMP | Internal temperature sensor voltage gain | –2 | mV/°C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
f(LOSC) | Operating frequency | 32.768 | kHz | |||
f(EIO) | Frequency error(1)(2) | TA = 0°C to 60°C | –1.5% | 0.25% | 1.5% | |
TA = –20°C to 70°C | –2.5% | 0.25% | 2.5% | |||
TA = –40°C to 85°C | –4% | 0.25% | 4% | |||
t(SXO) | Start-up time(3) | 500 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
f(LOSC) | Operating frequency | 8.389 | MHz | |||
f(EIO) | Frequency error(1)(2) | TA = 0°C to 60°C | –2% | 0.38% | 2% | |
TA = –20°C to 70°C | –3% | 0.38% | 3% | |||
TA = –40°C to 85°C | –4.5% | 0.38% | 4.5% | |||
t(SXO) | Start-up time(3) | 5 | ms |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
V(SR) | Differential input voltage range | V(SR) = V(SRP) – V(SRN) | –0.125 | 0.125 | V | |
V(SRP), V(SRN) | Input voltage range, V(SRP) and V(SRN) | –0.125 | 0.125 | V | ||
tSR_CONV | Conversion time | Single conversion | 1 | s | ||
Resolution | 14 | 15 | bits | |||
VOS(SR) | Input offset | 10 | µV | |||
INL | Integral nonlinearity error | ±0.007% | FSR(1) | |||
ZIN(SR) | Effective input resistance(2) | 2.5 | MΩ | |||
ILKG(SR) | Input leakage current(2) | 0.3 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIN((ADC) | ADC input voltage range for BAT measurement | Internal voltage divider inactive, internal VREF | 0.05 | 1 | V | |
Internal voltage divider activated, internal VREF | 0.05 | 4.5 | V | |||
ADC input voltage for TS pin measurement | 0 | VREG25 | V | |||
tADC_CONV(1) | Conversion time | Single conversion | 125 | ms | ||
Resolution | 14 | 15 | bits | |||
VOS(ADC) | Input offset | 1 | mV | |||
ZADC_TS | Effective input resistance (TS with internal pull-down activated)(1) | 5 | kΩ | |||
ZADC_BAT | Effective input resistance (BAT)(1) | When not measuring cell voltage (internal voltage divider inactive) | 8 | MΩ | ||
During measurement of cell voltage using internal divider (internal voltage divider active) | 100 | kΩ | ||||
ILKG(ADC) | Input leakage current(1) | 0.3 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tDR | Data retention(1) | 10 | Years | |||
Flash –programming write cycles(1) | 20,000 | Cycles | ||||
tWORDPROG | Word programming time(1) | 2 | ms | |||
ICCPROG | Flash-write supply current(1) | 5 | 10 | mA |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
tR | SCL/SDA rise time | 300 | ns | |||
tF | SCL/SDA fall time | 300 | ns | |||
tW(H) | SCL pulse width (high) | 600 | ns | |||
tW(L) | SCL pulse width (low) | 1.3 | µs | |||
tSU(STA) | Setup for repeated start | 600 | ns | |||
td(STA) | Start to first falling edge of SCL | 600 | ns | |||
tSU(DAT) | Data setup time | 100 | ns | |||
th(DAT) | Data hold time | 0 | ns | |||
tSU(STOP) | Setup time for stop | 600 | ns | |||
tBUF | Bus free time between stop and start | 66 | µs | |||
fSCL | Clock frequency | 400 | kHz |
The bq34110 device incorporates multiple capabilities to provide detailed and sophisticated information on single-cell and multi-cell battery packs. Several different battery chemistries are supported, including Li-Ion, LiFePO4, lead-acid (PbA), Nickel Metal Hydride (NiMH), and Nickel Cadmium (NiCd). The device integrates a gas gauge for monitoring battery charge level, an End-Of-Service (EOS) Determination function to evaluate when a battery is nearing the end of its usable life, a specialized WHr Charge Termination function to enable battery charging to a targeted energy capacity, a charge control scheme using direct pin control, SHA-1/HMAC-based authentication, and lifetime data logging functionality.
NOTE
Formatting Conventions in This Document:
Commands: italics with parentheses and no breaking spaces; for example, Control()
Data Flash: italics, bold, and breaking spaces; for example, Design Capacity
Register Bits and Flags: brackets only; for example, [TDA]
Data Flash Bits: italic and bold; for example, [XYZ1]
Modes and States: ALL CAPITALS; for example, UNSEALED mode
The bq34110 gas gauge uses Compensated End-of-Discharge Voltage (CEDV) technology to accurately predict the battery capacity and other operational characteristics of the battery, and can be interrogated by a host processor to provide cell information, such as remaining capacity, full charge capacity, and average current.
The integrated End-Of-Service (EOS) Determination function is specifically intended for applications where the battery is rarely discharged, such as in uninterruptible power supplies (UPS), enterprise server backup systems, and telecommunications backup modules. In such systems, the battery may remain in a fully (or near-fully) charged state for much of its lifetime, with it rarely or never undergoing a significant discharge. If the health of the battery in such a system is not monitored regularly, then it may degrade beyond the level required for a system backup/discharge event, and thus fail precisely at the time when it is needed most.
The EOS Determination function monitors the health of the battery through the use of infrequent Learning Phases, which involves a controlled discharge of ~1% capacity, and provides an alert to the system when the battery is approaching the end of its usable service. By coordinating battery charging with the Learning Phases, the battery capacity available to the system can be maintained above a preselected level to avoid compromising the ability for the battery to support a system discharge event.
The bq34110 device can support multi-cell battery configurations with maximum voltage up to 65 V through the use of external and internal resistive divider networks to reduce the voltage to an acceptable range for the device’s integrated ADC. These resistive dividers are actively controlled to avoid unnecessary power dissipation when not needed. The device integrates an internal temperature sensor as well as support for an external NTC thermistor, such as a Semitec 103AT or Mitsubishi BN35-3H103FB-50.
The battery current is monitored by measuring the voltage across a series resistor, RSENSE, which is placed in series with the battery pack and has a typical value of 5 mΩ to 20 mΩ. The bq34110 device integrates two ADCs, one of which is dedicated to current measurement, and the second used for measurement of several other parameters, including temperature and voltage.
Communication with the device is provided through an I2C interface, supporting rates up to 400 kHz. Dual ALERT pins are provided with programmable configuration, which enables them to be used for such functions as a host interrupt/alert or controlling the battery charger.
To minimize power consumption, the bq34110 gauge has several power modes: NORMAL, SNOOZE, and SLEEP, which are under register or algorithm control. In addition, a separate chip enable (CE) pin is provided to control the internal LDO, which powers the bq34110 internal circuitry, and can put the device into SHUTDOWN mode.
Information is accessed through a series of commands called Data Commands, which are indicated by the general format Command(). These commands are used to read and write information in the bq34110 device’s control and status registers, as well as its data flash locations.
Commands are sent from the host to the bq34110 device via I2C and can be executed during application development, pack manufacture, or end-equipment operation. Cell information is stored in the bq34110 device in non-volatile flash memory. Many of the data flash locations are accessible during application development and pack manufacture. They cannot, generally, be accessed directly during end-equipment operation. Access to these locations is achieved by using the bq34110 device’s companion evaluation software, through individual commands, or through a sequence of data flash access commands. To access a desired data flash location, the correct data flash subclass and offset must be known.
The bq34110 device provides 32 bytes of user-programmable data flash memory. This data space is accessed through a data flash interface. For specifics on accessing the data flash, see the bq34110 Technical Reference Manual (SLUUBF7).
A SHA-1/HMAC-based battery pack authentication feature is also implemented on the bq34110 device. When the device is in UNSEALED mode, authentication keys can be (re)assigned. A scratch pad area is used to receive challenge information from a host and to export SHA-1/HMAC encrypted responses. For more information on authentication, see the bq34110 Technical Reference Manual (SLUUBF7).
The bq34110 device supports the standard I2C read, incremental read, one-byte write quick read, and functions. The 7-bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as 1010101. The 8-bit device address is therefore 0xAA or 0xAB for write or read, respectively.
The “quick read” returns data at the address indicated by the address pointer. The address pointer, a register internal to the I2C communication engine, increments whenever data is acknowledged by the device or the I2C master. “Quick writes” function in the same manner and are a convenient means of sending multiple bytes to consecutive command locations (such as 2-byte commands that require two bytes of data).
The I2C engine releases both SDA and SCL if the I2C bus is held low for a time programmed in data flash. If the device were holding the lines, releasing them frees the master to drive the lines.
Detailed examples of I2C transactions accessing gauge data can be found in the Using I2C Communication with the bq275xx Series of Fuel Gauges Application Report (SLUA467).
The bq34110 device has four functional power modes: NORMAL, SNOOZE, SLEEP, and SHUTDOWN, based on firmware and/or host control.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The bq34110 gas gauge is a highly configurable device with multiple features that can be used individually or simultaneously (with some restrictions). The CEDV gas gauging function together with its support for an external voltage divider allows gauging of high voltage, multi-cell battery configurations of various chemistries. The EOS Determination function is intended for rarely discharged applications and evaluates the condition of the battery without requiring conventional maintenance cycles. These and additional features are described in detail in the bq34110 Technical Reference Manual (SLUUBF7).
Figure 11 is a simplified schematic of the bq34110 system used in a multi-cell configuration.
Figure 12 shows the schematic of the bq34110 EVM, and depicts how the device can be used in the system.
The bq34110 device supports several circuit configuration options that can be decided upon during the system design phase. Using the device with a single-cell battery versus a multi-cell configuration determines if there is a need for a battery divider and associated control using the VEN pin (as shown in Figure 11). The functions used within the bq34110 device also determine the pin usage, with the device incorporating flexibility to reuse pins for other purposes if the system configuration permits. For example, if a single-cell configuration is selected, then the VEN pin can be used as part of a direct charge control scheme. Similarly, the LEN, ALERT1, and/or ALERT2 pins can also be repurposed to support direct charge control. For additional design guidelines, refer to the bq34110 EVM User’s Guide (SLUUBI1).
A ceramic capacitor at the input to the BAT pin is used to bypass AC voltage ripple to ground, greatly reducing its influence on battery voltage measurements. It proves most effective in applications with load profiles that exhibit high-frequency current pulses (that is, cell phones) but is recommended for use in all applications to reduce noise on this sensitive high-impedance measurement node. If the device is used in a multi-cell configuration with an external resistive voltage divider, it is recommended that the resistors used therein be selected with temperature coefficient of resistance (TCR) of 75-ppm or below. More detail on the design of the voltage divider network is discussed in the bq34110 Technical Reference Manual (SLUUBF7).
The filter network at the input to the coulomb counter is intended to improve differential mode rejection of voltage measured across the sense resistor. These components should be placed as close as possible to the coulomb counter inputs, and the routing of the differential traces length-matched to best minimize impedance mismatch-induced measurement errors.
Any variation encountered in the resistance present between the SRP and SRN pins of the fuel gauge will affect the resulting differential voltage, and derived current, it senses. As such, it is recommended to select a sense resistor with minimal tolerance and temperature coefficient of resistance (TCR) characteristics. The standard recommendation based on the best compromise between performance and price is a 1% tolerance, 75-ppm drift sense resistor with a 1-W power rating.
Similar to the BAT pin, a ceramic decoupling capacitor for the TS pin is used to bypass AC voltage ripple away from the high-impedance ADC input, minimizing measurement error. It should be placed as close as possible to the respective input pin for optimal filtering performance.
The fuel gauge temperature sensing circuitry is designed to work with a negative temperature coefficient-type (NTC) thermistor with a characteristic 10-kΩ resistance at room temperature (25°C). The default curve-fitting coefficients configured in the fuel gauge specifically assume a 103AT-2 type thermistor profile and so that is the default recommendation for thermistor selection purposes. Moving to a separate thermistor resistance profile (for example, JT-2 or others) requires an update to the default thermistor coefficients in data flash to ensure highest accuracy temperature measurement performance.
A ceramic capacitor is placed at the input to the fuel gauge internal LDO to increase power supply rejection (PSR) and improve effective line regulation. It ensures that voltage ripple is rejected to ground instead of coupling into the internal supply rails of the fuel gauge.
A ceramic capacitor is also needed at the output of the internal LDO to provide a current reservoir for fuel gauge load peaks during high peripheral utilization. It acts to stabilize the regulator output and reduce core voltage ripple inside the fuel gauge.
Power supply requirements for the bq34110 device are simplified due to the presence of the internal LDO-voltage regulation. The REGIN pin accepts any voltage level between 2.7 V and 4.5 V, which is optimum for a single-cell Li-Ion application. For higher battery voltage applications, a simple preregulator can be provided to power the bq34110 device. Decoupling the REGIN pin should be done with a 0.1-μF 10% ceramic X5R capacitor placed close to the device. While the preregulator circuit is not critical, special attention should be paid to its quiescent current and power dissipation. The input voltage should handle the maximum battery stack voltage. The output voltage can be centered within the 2.7-V to 4.5-V range as recommended for the REGIN pin.
For high stack count applications, a commercially available LDO is often the best quality solution, but comes with a cost tradeoff. To lower the BOM cost, the following approaches are recommended.
In Figure 17, Q1 is used to drop the battery stack voltage to roughly 4 V to power the bq34110 device's REGIN pin. To avoid unwanted quiescent current consumption, R1 should be set as high as is practical. It is recommended to use a low-current Zener diode.
Alternatively, if the range of a high-voltage battery stack can be well-defined, a simple source follower based on a resistive divider can be used to lower the BOM cost and the quiescent current. For example:
Attention to layout is critical to the success of any battery management circuit board. The mixture of high-current paths with an ultralow-current microcontroller creates the potential for design issues that are not always trivial to solve. Some of the key areas of concern are described in the following sections and can help to enable success.
Power supply decoupling from REG25 to ground is important for optimal operation of the gas gauge. To keep the loop area small, place this capacitor next to the IC and use the shortest possible traces. A large loop area renders the capacitor useless and forms a small-loop antenna for noise pickup. Ideally, the traces on each side of the capacitor should be the same length and run in the same direction to avoid differential noise during ESD. If possible, place a via near the VSS pin to a ground plane layer.
Power supply decoupling for the gas gauge requires 0.1-μF ceramic capacitors for the BAT and REGIN pins. These should be placed reasonably close to the IC without using long traces back to VSS. The LDO voltage regulator, whether external or internal to the main IC, requires a 1-μF ceramic capacitor to be placed fairly close to the regulation output pin (REG25). This capacitor is for amplifier loop stabilization and as an energy well for the 2.5-V supply.
5.6-V Zener diodes are included on the I2C lines to protect the communication pins of the gas gauge from ESD. These diodes should be located as close as possible to the pack connector. The grounded end of these Zener diodes should be returned to the PACK(–) node rather than to the low-current digital ground system. This way, ESD is diverted away from the sensitive electronics as much as possible.
The gas gauge requires a low-current ground system separate from the high-current PACK(–) path. ESD ground is defined along the high-current path from the PACK(–) terminal to the sense resistor. It is important that the low-current ground systems only connect to the PACK(–) path at the sense resistor Kelvin pick-off point. It is recommended to use an optional inner layer ground plane for the low-current ground system.
In Figure 19, the green area shows an example of using the low-current ground as a shield for the gas gauge circuit. Notice how it is kept separate from the high-current ground, which is shown in red. The high current path is joined with the low-current path only at one point, shown with the small blue connection between the two planes.
Kelvin voltage sensing is very important to accurately measure current and cell voltage. Note that in Figure 19 the differential connections at the sense resistor do not add any voltage drop across the copper etch that carries the high current path through the sense resistor.
Although the most important component for board offset reduction is the decoupling capacitor for REGIN, additional benefit is possible by using this recommended pattern for the coulomb counter differential low-pass filter network.
Maintain the symmetrical placement pattern shown for optimum current offset performance. Use symmetrical shielded differential traces, if possible, from the sense resistor to the 100-Ω resistors, as shown in Figure 20.
Protect the communication lines from ESD with a spark gap at the connector. Figure 21 shows the recommended pattern with its 0.2-mm spacing between the points.
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