SLUSAU1C May 2012 – May 2021 BQ34Z100
PRODUCTION DATA
Some BQ34Z100 pins are configured via the Pack Configuration data flash register, as indicated in Table 7-14. This register is programmed/read via the methods described in Section 7.2.3.1. The register is located at subclass = 64, offset = 0.
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
SOH_DISP | RSOC_HOLD | FF_NEAR_EDV | SleepWakeCHG | LOCK_0 | RELAX_JUMP_OK | RELAX_SMOOTH_OK | SMOOTH |
SOH_DISP: | Enables State-of-Health Display | |||
RSOC_HOLD: | Enables RSOC Hold Feature preventing RSOC from increasing during discharge | |||
SleepWakeCHG: | Enable for faster sampling in SLEEP mode. Default setting is recommended. | |||
LOCK_0: | Keep RemainingCapacity() and RelativeStateOfCharge() jumping back during relaxation after 0 was reached during discharge. | |||
RELAX_JUMP_OK: | Allows RSOC jump during RELAX mode | |||
RELAX_SMOOTH_OK: | Smooth RSOC during RELAX mode | |||
SMOOTH: | Enabled RSOC Smoothing |