The Texas Instruments bq4050 device, incorporating Compensated End-of-Discharge Voltage (CEDV) technology, is a highly integrated, accurate, 1-series to 4-series cell gas gauge and protection solution, enabling autonomous charger control and cell balancing.
The bq4050 device provides a fully integrated pack-based solution with a flash programmable custom reduced instruction-set CPU (RISC), safety protection, and authentication for Li-Ion and Li-Polymer battery packs.
The bq4050 gas gauge communicates via an SMBus-compatible interface and combines an ultra-low power, high-speed TI bqBMP processor, high-accuracy analog measurement capabilities, integrated flash memory, an array of peripheral and communication ports, an N-CH FET drive, and a SHA-1 Authentication transform responder into a complete, high-performance battery management solution.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
bq4050 | VQFN (32) | 4.00 mm × 4.00 mm |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
PBI | 1 | P(1) | Power supply backup input pin |
VC4 | 2 | IA | Sense voltage input pin for the most positive cell, and balance current input for the most positive cell |
VC3 | 3 | IA | Sense voltage input pin for the second most positive cell, balance current input for the second most positive cell, and return balance current for the most positive cell |
VC2 | 4 | IA | Sense voltage input pin for the third most positive cell, balance current input for the third most positive cell, and return balance current for the second most positive cell |
VC1 | 5 | IA | Sense voltage input pin for the least positive cell, balance current input for the least positive cell, and return balance current for the third most positive cell |
SRN | 6 | I | Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN where SRP is the top of the sense resistor. |
NC | 7 | — | Not internally connected. Connect to VSS. |
SRP | 8 | I | Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN where SRP is the top of the sense resistor. |
VSS | 9 | P | Device ground |
TS1 | 10 | IA | Temperature sensor 1 thermistor input pin |
TS2 | 11 | IA | Temperature sensor 2 thermistor input pin |
TS3 | 12 | IA | Temperature sensor 3 thermistor input pin |
TS4 | 13 | IA | Temperature sensor 4 thermistor input pin |
NC | 14 | — | Not internally connected. Connect to VSS. |
BTP_INT | 15 | O | Battery Trip Point (BTP) interrupt output |
PRES or SHUTDN | 16 | I | Host system present input for removable battery pack or emergency system shutdown input for embedded packs |
DISP | 17 | — | Display control for LEDs |
SMBD | 18 | I/OD | SMBus data pin |
SMBC | 19 | I/OD | SMBus clock pin |
LEDCNTLA | 20 | — | LED display segment that drives the external LEDs depending on the firmware configuration |
LEDCNTLB | 21 | — | LED display segment that drives the external LEDs depending on the firmware configuration |
LEDCNTLC | 22 | — | LED display segment that drives the external LEDs depending on the firmware configuration |
PTC | 23 | IA | Safety PTC thermistor input pin. To disable, connect PTC and PTCEN to VSS. |
PTCEN | 24 | IA | Safety PTC thermistor enable input pin. Connect to BAT. To disable, connect PTC and PTCEN to VSS. |
FUSE | 25 | O | Fuse drive output pin |
VCC | 26 | P | Secondary power supply input |
PACK | 27 | IA | Pack sense input pin |
DSG | 28 | O | NMOS Discharge FET drive output pin |
NC | 29 | — | Not internally connected. Connect to VSS. |
PCHG | 30 | O | PMOS Precharge FET drive output pin |
CHG | 31 | O | NMOS Charge FET drive output pin |
BAT | 32 | P | Primary power supply input pin |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage range, VCC | BAT, VCC, PBI | –0.3 | 30 | V |
Input voltage range, VIN | PACK, SMBC, SMBD, PRES or SHUTDN, BTP_INT, DISP | –0.3 | 30 | V |
TS1, TS2, TS3, TS4 | –0.3 | VREG + 0.3 | V | |
PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC | –0.3 | VBAT + 0.3 | V | |
SRP, SRN | –0.3 | 0.3 | V | |
VC4 | VC3 – 0.3 | VC3 + 8.5 V, or VSS + 30 | V | |
VC3 | VC2 – 0.3 | VC2 + 8.5 V, or VSS + 30 | V | |
VC2 | VC1 – 0.3 | VC1 + 8.5 V, or VSS + 30 | V | |
VC1 | VSS – 0.3 | VSS + 8.5 V, or VSS + 30 V | V | |
Output voltage range, VO | CHG, DSG | –0.3 | 32 | |
PCHG, FUSE | –0.3 | 30 | V | |
Maximum VSS current, ISS | 50 | mA | ||
TSTG | Storage temperature | –65 | 150 | °C |
Lead temperature (soldering, 10 s), TSOLDER | 300 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
VCC | Supply voltage | BAT, VCC, PBI | 2.2 | 26 | V | ||
VSHUTDOWN– | Shutdown voltage | VPACK < VSHUTDOWN– | 1.8 | 2.0 | 2.2 | V | |
VSHUTDOWN+ | Start-up voltage | VPACK > VSHUTDOWN– + VHYS | 2.05 | 2.25 | 2.45 | V | |
VHYS | Shutdown voltage hysteresis | VSHUTDOWN+ – VSHUTDOWN– | 250 | mV | |||
VIN | Input voltage range | PACK, SMBC, SMBD, PRES, BTP_IN, DISP | 26 | V | |||
TS1, TS2, TS3, TS4 | VREG | ||||||
PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC | VBAT | ||||||
SRP, SRN | –0.2 | 0.2 | |||||
VC4 | VVC3 | VVC3 + 5 | |||||
VC3 | VVC2 | VVC2 + 5 | |||||
VC2 | VVC1 | VVC1 + 5 | |||||
VC1 | VVSS | VVSS + 5 | |||||
VO | Output voltage range | CHG, DSG, PCHG, FUSE | 26 | V | |||
CPBI | External PBI capacitor | 2.2 | µF | ||||
TOPR | Operating temperature | –40 | 85 | °C |
THERMAL METRIC(1) | bq4050 | UNIT | ||
---|---|---|---|---|
RSM (QFN) | ||||
32 PINS | ||||
RθJA, High K | Junction-to-ambient thermal resistance | 47.4 | °C/W | |
RθJC(top) | Junction-to-case(top) thermal resistance | 40.3 | °C/W | |
RθJB | Junction-to-board thermal resistance | 14.7 | °C/W | |
ψJT | Junction-to-top characterization parameter | 0.8 | °C/W | |
ψJB | Junction-to-board characterization parameter | 14.4 | °C/W | |
RθJC(bottom) | Junction-to-case(bottom) thermal resistance | 3.8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
INORMAL | NORMAL mode | CHG on. DSG on, no Flash write | 336 | µA | |||
ISLEEP | SLEEP mode | CHG off, DSG on, no SBS communication | 75 | µA | |||
CHG off, DSG off, no SBS communication | 52 | ||||||
ISHUTDOWN | SHUTDOWN mode | 1.6 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VSWITCHOVER– | BAT to VCC switchover voltage | VBAT < VSWITCHOVER– | 1.95 | 2.1 | 2.2 | V |
VSWITCHOVER+ | VCC to BAT switchover voltage | VBAT > VSWITCHOVER– + VHYS | 2.9 | 3.1 | 3.25 | V |
VHYS | Switchover voltage hysteresis | VSWITCHOVER+ – VSWITCHOVER– | 1000 | mV | ||
ILKG | Input Leakage current | BAT pin, BAT = 0 V, VCC = 25 V, PACK = 25 V | 1 | µA | ||
PACK pin, BAT = 25 V, VCC = 0 V, PACK = 0 V | 1 | |||||
BAT and PACK terminals, BAT = 0 V, VCC = 0 V, PACK = 0 V, PBI = 25 V | 1 | |||||
RPD | Internal pulldown resistance | PACK | 30 | 40 | 50 | kΩ |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VREGIT– | Negative-going voltage input | VREG | 1.51 | 1.55 | 1.59 | V |
VHYS | Power-on reset hysteresis | VREGIT+ – VREGIT– | 70 | 100 | 130 | mV |
tRST | Power-on reset time | 200 | 300 | 400 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tWDT | AFE watchdog timeout | tWDT = 500 | 372 | 500 | 628 | ms |
tWDT = 1000 | 744 | 1000 | 1256 | |||
tWDT = 2000 | 1488 | 2000 | 2512 | |||
tWDT = 4000 | 2976 | 4000 | 5024 | |||
tWAKE | AFE wake timer | tWAKE = 250 | 186 | 250 | 314 | ms |
tWAKE = 500 | 372 | 500 | 628 | |||
tWAKE = 1000 | 744 | 1000 | 1256 | |||
tWAKE = 512 | 1488 | 2000 | 2512 | |||
tFETOFF | FET off delay after reset | tFETOFF = 512 | 409 | 512 | 614 | ms |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VWAKE | Wake voltage threshold | VWAKE = ±0.625 mV | ±0.3 | ±0.625 | ±0.9 | mV |
VWAKE = ±1.25 mV | ±0.6 | ±1.25 | ±1.8 | |||
VWAKE = ±2.5 mV | ±1.2 | ±2.5 | ±3.6 | |||
VWAKE = ±5 mV | ±2.4 | ±5.0 | ±7.2 | |||
VWAKE(DRIFT) | Temperature drift of VWAKE accuracy | 0.5% | °C | |||
tWAKE | Time from application of current to wake interrupt | 700 | µs | |||
tWAKE(SU) | Wake comparator startup time | 500 | 1000 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
K | Scaling factor | VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3 | 0.1980 | 0.2000 | 0.2020 | — |
BAT–VSS, PACK–VSS | 0.049 | 0.050 | 0.051 | |||
VREF2 | 0.490 | 0.500 | 0.510 | |||
VIN | Input voltage range | VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3 | –0.2 | 5 | V | |
BAT–VSS, PACK–VSS | –0.2 | 20 | ||||
ILKG | Input leakage current | VC1, VC2, VC3, VC4, cell balancing off, cell detach detection off, ADC multiplexer off | 1 | µA | ||
RCB | Internal cell balance resistance | RDS(ON) for internal FET switch at 2 V < VDS < 4 V | 200 | Ω | ||
ICD | Internal cell detach check current | VCx > VSS + 0.8 V | 30 | 50 | 70 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIH | Input voltage high | SMBC, SMBD, VREG = 1.8 V | 1.3 | V | |||
VIL | Input voltage low | SMBC, SMBD, VREG = 1.8 V | 0.8 | V | |||
VOL | Output low voltage | SMBC, SMBD, VREG = 1.8 V, IOL = 1.5 mA | 0.4 | V | |||
CIN | Input capacitance | 5 | pF | ||||
ILKG | Input leakage current | 1 | µA | ||||
RPD | Pulldown resistance | 0.7 | 1.0 | 1.3 | MΩ |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIH | High-level input | 1.3 | V | |||
VIL | Low-level input | 0.55 | V | |||
VOH | Output voltage high | VBAT > 5.5 V, IOH = –0 µA | 3.5 | V | ||
VBAT > 5.5 V, IOH = –10 µA | 1.8 | |||||
VOL | Output voltage low | IOL = 1.5 mA | 0.4 | V | ||
CIN | Input capacitance | 5 | pF | |||
ILKG | Input leakage current | 1 | µA | |||
RO | Output reverse resistance | Between PRES or BTP_INT or DISP and PBI | 8 | kΩ |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIH | High-level input | 1.45 | V | |||
VIL | Low-level input | 0.55 | V | |||
VOH | Output voltage high | VBAT > 3.0 V, IOH = –22.5 mA | VBAT – 1.6 | V | ||
VOL | Output voltage low | IOL = 1.5 mA | 0.4 | V | ||
ISC | High level output current protection | –30 | –45 | –6 0 | mA | |
IOL | Low level output current | VBAT > 3.0 V, VOH = 0.4 V | 15.75 | 22.5 | 29.25 | mA |
ILEDCNTLx | Current matching between LEDCNTLx | VBAT = VLEDCNTLx + 2.5 V | ±1% | |||
CIN | Input capacitance | 20 | pF | |||
ILKG | Input leakage current | 1 | µA | |||
fLEDCNTLx | Frequency of LED pattern | 124 | Hz |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Input voltage range | –0.1 | 0.1 | V | ||
Full scale range | –VREF1/10 | VREF1/10 | V | ||
Integral nonlinearity(1) | 16-bit, best fit over input voltage range | ±5.2 | ±22.3 | LSB | |
Offset error | 16-bit, Post-calibration | ±5 | ±10 | µV | |
Offset error drift | 15-bit + sign, Post-calibration | 0.2 | 0.3 | µV/°C | |
Gain error | 15-bit + sign, over input voltage range | ±0.2% | ±0.8% | FSR | |
Gain error drift | 15-bit + sign, over input voltage range | 150 | PPM/°C | ||
Effective input resistance | 2.5 | MΩ |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Conversion time | Single conversion | 250 | ms | ||
Effective resolution | Single conversion | 15 | Bits |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Input voltage range | Internal reference (VREF1) | –0.2 | 1 | V | |
External reference (VREG) | –0.2 | 0.8 × VREG | |||
Full scale range | VFS = VREF1 or VREG | –VFS | VFS | V | |
Integral nonlinearity(1) | 16-bit, best fit, –0.1 V to 0.8 × VREF1 | ±6.6 | LSB | ||
16-bit, best fit, –0.2 V to –0.1 V | ±13.1 | ||||
Offset error(2) | 16-bit, Post-calibration, VFS = VREF1 | ±67 | ±157 | µV | |
Offset error drift | 16-bit, Post-calibration, VFS = VREF1 | 0.6 | 3 | µV/°C | |
Gain error | 16-bit, –0.1 V to 0.8 × VFS | ±0.2% | ±0.8% | FSR | |
Gain error drift | 16-bit, –0.1 V to 0.8 × VFS | 150 | PPM/°C | ||
Effective input resistance | 8 | MΩ |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Conversion time | Single conversion | 31.25 | ms | ||
Single conversion | 15.63 | ||||
Single conversion | 7.81 | ||||
Single conversion | 1.95 | ||||
Resolution | No missing codes | 16 | Bits | ||
Effective resolution | With sign, tCONV = 31.25 ms | 14 | 15 | Bits | |
With sign, tCONV = 15.63 ms | 13 | 14 | |||
With sign, tCONV = 7.81 ms | 11 | 12 | |||
With sign, tCONV = 1.95 ms | 9 | 10 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Output voltage ratio | RatioDSG = (VDSG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V, 10 MΩ between PACK and DSG | 2.133 | 2.333 | 2.433 | — | ||
RatioCHG = (VCHG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V, 10 MΩ between BAT and CHG | 2.133 | 2.333 | 2.433 | ||||
V(FETON) | Output voltage, CHG and DSG on | VDSG(ON) = VDSG – VBAT, 4.92 V ≤ VBAT ≤ 18 V, 10 MΩ between PACK and DSG | 10.5 | 11.5 | 12 | V | |
VCHG(ON) = VCHG – VBAT, 4.92 V ≤ VBAT ≤ 18 V, 10 MΩ between BAT and CHG | 10.5 | 11.5 | 12 | ||||
V(FETOFF) | Output voltage, CHG and DSG off | VDSG(OFF) = VDSG – VPACK, 10 MΩ between PACK and DSG | –0.4 | 0.4 | V | ||
VCHG(OFF) = VCHG – VBAT, 10 MΩ between BAT and CHG | –0.4 | 0.4 | |||||
tR | Rise time | VDSG from 0% to 35% VDSG(ON)(TYP), VBAT ≥ 2.2 V, CL = 4.7 nF between DSG and PACK, 5.1 kΩ between DSG and CL, 10 MΩ between PACK and DSG | 200 | 500 | µs | ||
VCHG from 0% to 35% VCHG(ON)(TYP), VBAT ≥ 2.2 V, CL = 4.7 nF between CHG and BAT, 5.1 kΩ between CHG and CL, 10 MΩ between BAT and CHG | 200 | 500 | |||||
tF | Fall time | VDSG from VDSG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7 nF between DSG and PACK, 5.1 kΩ between DSG and CL, 10 MΩ between PACK and DSG | 40 | 300 | µs | ||
VCHG from VCHG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7 nF between CHG and BAT, 5.1 kΩ between CHG and CL, 10 MΩ between BAT and CHG | 40 | 200 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
V(FETON) | Output voltage, PCHG on | VPCHG(ON) = VVCC – VPCHG, 10 MΩ between VCC and PCHG | 6 | 7 | 8 | V | |
V(FETOFF) | Output voltage, PCHG off | VPCHG(OFF) = VVCC – VPCHG, 10 MΩ between VCC and PCHG | –0.4 | 0.4 | V | ||
tR | Rise time | VPCHG from 10% to 90% VPCHG(ON)(TYP), VVCC ≥ 8 V, CL = 4.7 nF between PCHG and VCC, 5.1 kΩ between PCHG and CL, 10 MΩ between VCC and CHG | 40 | 200 | µs | ||
tF | Fall time | VPCHG from 90% to 10% VPCHG(ON)(TYP), VCC ≥ 8 V, CL = 4.7 nF between PCHG and VCC, 5.1 kΩ between PCHG and CL, 10 MΩ between VCC and CHG | 40 | 200 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | Output voltage high | VBAT ≥ 8 V, CL = 1 nF, IAFEFUSE = 0 µA | 6 | 7 | 8.65 | V | |
VBAT < 8 V, CL = 1 nF, IAFEFUSE = 0 µA | VBAT – 0.1 | VBAT | |||||
VIH | High-level input | 1.5 | 2.0 | 2.5 | V | ||
IAFEFUSE(PU) | Internal pullup current | VBAT ≥ 8 V, VAFEFUSE = VSS | 150 | 330 | nA | ||
RAFEFUSE | Output impedance | 2 | 2.6 | 3.2 | kΩ | ||
CIN | Input capacitance | 5 | pF | ||||
tDELAY | Fuse trip detection delay | 128 | 256 | µs | |||
tRISE | Fuse output rise time | VBAT ≥ 8 V, CL = 1 nF, VOH = 0 V to 5 V | 5 | 20 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VTEMP | Internal temperature sensor voltage drift | VTEMPP | –1.9 | –2.0 | –2.1 | mV/°C |
VTEMPP – VTEMPN, assured by design | 0.177 | 0.178 | 0.179 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIN | Input voltage range | TS1, TS2, TS3, TS4, VBIAS = VREF1 | –0.2 | 0.8 × VREF1 | V | |
TS1, TS2, TS3, TS4, VBIAS = VREG | –0.2 | 0.8 × VREG | ||||
RNTC(PU) | Internal pullup resistance | TS1, TS2, TS3, TS4 | 14.4 | 18 | 21.6 | kΩ |
RNTC(DRIFT) | Resistance drift over temperature | TS1, TS2, TS3, TS4 | –360 | –280 | –200 | PPM/°C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
RPTC(TRIP) | PTC trip resistance | 1.2 | 2.5 | 3.95 | MΩ | |
VPTC(TRIP) | PTC trip voltage | VPTC(TRIP) = VPTCEN – VPTC | 200 | 500 | 890 | mV |
IPTC | Internal PTC current bias | TA = –40°C to 110°C | 200 | 290 | 350 | nA |
tPTC(DELAY) | PTC delay time | TA = –40°C to 110°C | 40 | 80 | 145 | ms |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VREG | Regulator voltage | 1.6 | 1.8 | 2.0 | V | ||
ΔVO(TEMP) | Regulator output over temperature | ΔVREG/ΔTA, IREG = 10 mA | ±0.25% | ||||
ΔVO(LINE) | Line regulation | ΔVREG/ΔVBAT, VBAT = 10 mA | –0 .6% | 0.5% | |||
ΔVO(LOAD) | Load regulation | ΔVREG/ΔIREG, IREG = 0 mA to 10 mA | –1.5% | 1.5% | |||
IREG | Regulator output current limit | VREG = 0.9 × VREG(NOM), VIN > 2.2 V | 20 | mA | |||
ISC | Regulator short-circuit current limit | VREG = 0 × VREG(NOM) | 25 | 40 | 55 | mA | |
PSRRREG | Power supply rejection ratio | ΔVBAT/ΔVREG, IREG = 10 mA ,VIN > 2.5 V, f = 10 Hz | 40 | dB | |||
VSLEW | Slew rate enhancement voltage threshold | VREG | 1.58 | 1.65 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fHFO | Operating frequency | 16.78 | MHz | |||
fHFO(ERR) | Frequency error | TA = –20°C to 70°C, includes frequency drift | –2.5% | ±0.25% | 2.5% | |
TA = –40°C to 85°C, includes frequency drift | –3.5% | ±0.25% | 3.5% | |||
tHFO(SU) | Start-up time | TA = –20°C to 85°C, oscillator frequency within +/–3% of nominal | 4 | ms | ||
oscillator frequency within +/–3% of nominal | 100 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fLFO | Operating frequency | 262.144 | kHz | |||
fLFO(ERR) | Frequency error | TA = –20°C to 70°C, includes frequency drift | –1.5% | ±0.25% | 1.5% | |
TA = –40°C to 85°C, includes frequency drift | –2.5 | ±0.25 | 2.5 | |||
fLFO(FAIL) | Failure detection frequency | 30 | 80 | 100 | kHz |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VREF1 | Internal reference voltage | TA = 25°C, after trim | 1.21 | 1.215 | 1.22 | V |
VREF1(DRIFT) | Internal reference voltage drift | TA = 0°C to 60°C, after trim | ±50 | PPM/°C | ||
TA = –40°C to 85°C, after trim | ±80 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VREF2 | Internal reference voltage | TA = 25°C, after trim | 1.22 | 1.225 | 1.23 | V |
VREF2(DRIFT) | Internal reference voltage drift | TA = 0°C to 60°C, after trim | ±50 | PPM/°C | ||
TA = –40°C to 85°C, after trim | ±80 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Data retention | 10 | Years | ||||
Flash programming write cycles | 1000 | Cycles | ||||
tPROGWORD | Word programming time | TA = –40°C to 85°C | 40 | µs | ||
tMASSERASE | Mass-erase time | TA = –40°C to 85°C | 40 | ms | ||
tPAGEERASE | Page-erase time | TA = –40°C to 85°C | 40 | ms | ||
IFLASHREAD | Flash-read current | TA = –40°C to 85°C | 2 | mA | ||
IFLASHWRITE | Flash-write current | TA = –40°C to 85°C | 5 | mA | ||
IFLASHERASE | Flash-erase current | TA = –40°C to 85°C | 15 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Data retention | 10 | Years | ||||
Flash programming write cycles | 20000 | Cycles | ||||
tPROGWORD | Word programming time | TA = –40°C to 85°C | 40 | µs | ||
tMASSERASE | Mass-erase time | TA = –40°C to 85°C | 40 | ms | ||
tPAGEERASE | Page-erase time | TA = –40°C to 85°C | 40 | ms | ||
IFLASHREAD | Flash-read current | TA = –40°C to 85°C | 1 | mA | ||
IFLASHWRITE | Flash-write current | TA = –40°C to 85°C | 5 | mA | ||
IFLASHERASE | Flash-erase current | TA = –40°C to 85°C | 15 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOCD | OCD detection threshold voltage range | VOCD = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 | –16.6 | –100 | mV | ||
VOCD = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 | –8.3 | –50 | |||||
ΔVOCD | OCD detection threshold voltage program step | VOCD = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 | –5.56 | mV | |||
VOCD = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 | –2.78 | ||||||
VSCC | SCC detection threshold voltage range | VSCC = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 | 44.4 | 200 | mV | ||
VSCC = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 | 22.2 | 100 | |||||
ΔVSCC | SCC detection threshold voltage program step | VSCC = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 | 22.2 | mV | |||
VSCC = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 | 11.1 | ||||||
VSCD1 | SCD1 detection threshold voltage range | VSCD1 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 | –44.4 | –200 | mV | ||
VSCD1 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 | –22.2 | –100 | |||||
ΔVSCD1 | SCD1 detection threshold voltage program step | VSCD1 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 | –22.2 | mV | |||
VSCD1 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 | –11.1 | ||||||
VSCD2 | SCD2 detection threshold voltage range | VSCD2 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 | –44.4 | –200 | mV | ||
VSCD2 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 | –22.2 | –100 | |||||
ΔVSCD2 | SCD2 detection threshold voltage program step | VSCD2 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 | –22.2 | mV | |||
VSCD2 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 | –11.1 | ||||||
VOFFSET | OCD, SCC, and SCDx offset error | Post-trim | –2.5 | 2.5 | mV | ||
VSCALE | OCD, SCC, and SCDx scale error | No trim | –10% | 10% | |||
Post-trim | –5% | 5% |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tOCD | OCD detection delay time | 1 | 31 | ms | ||
ΔtOCD | OCD detection delay time program step | 2 | ms | |||
tSCC | SCC detection delay time | 0 | 915 | µs | ||
ΔtSCC | SCC detection delay time program step | 61 | µs | |||
tSCD1 | SCD1 detection delay time | AFE PROTECTION CONTROL[SCDDx2] = 0 | 0 | 915 | µs | |
AFE PROTECTION CONTROL[SCDDx2] = 1 | 0 | 1850 | ||||
ΔtSCD1 | SCD1 detection delay time program step | AFE PROTECTION CONTROL[SCDDx2] = 0 | 61 | µs | ||
AFE PROTECTION CONTROL[SCDDx2] = 1 | 121 | |||||
tSCD2 | SCD2 detection delay time | AFE PROTECTION CONTROL[SCDDx2] = 0 | 0 | 458 | µs | |
AFE PROTECTION CONTROL[SCDDx2] = 1 | 0 | 915 | ||||
ΔtSCD2 | SCD2 detection delay time program step | AFE PROTECTION CONTROL[SCDDx2] = 0 | 30.5 | µs | ||
AFE PROTECTION CONTROL[SCDDx2] = 1 | 61 | |||||
tDETECT | Current fault detect time | VSRP – VSRN = VT – 3 mV for OCD, SCD1, and SC2, VSRP – VSRN = VT + 3 mV for SCC | 160 | µs | ||
tACC | Current fault delay time accuracy | Max delay setting | –10% | 10% |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
fSMB | SMBus operating frequency | SLAVE mode, SMBC 50% duty cycle | 10 | 100 | kHz | |
fMAS | SMBus master clock frequency | MASTER mode, no clock low slave extend | 51.2 | kHz | ||
tBUF | Bus free time between start and stop | 4.7 | µs | |||
tHD(START) | Hold time after (repeated) start | 4.0 | µs | |||
tSU(START) | Repeated start setup time | 4.7 | µs | |||
tSU(STOP) | Stop setup time | 4.0 | µs | |||
tHD(DATA) | Data hold time | 300 | ns | |||
tSU(DATA) | Data setup time | 250 | ns | |||
tTIMEOUT | Error signal detect time | 25 | 35 | ms | ||
tLOW | Clock low period | 4.7 | µs | |||
tHIGH | Clock high period | 4.0 | 50 | µs | ||
tR | Clock rise time | 10% to 90% | 1000 | ns | ||
tF | Clock fall time | 90% to 10% | 300 | ns | ||
tLOW(SEXT) | Cumulative clock low slave extend time | 25 | ms | |||
tLOW(MEXT) | Cumulative clock low master extend time | 10 | ms |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
fSMBXL | SMBus XL operating frequency | SLAVE mode | 40 | 400 | kHz | |
tBUF | Bus free time between start and stop | 4.7 | µs | |||
tHD(START) | Hold time after (repeated) start | 4.0 | µs | |||
tSU(START) | Repeated start setup time | 4.7 | µs | |||
tSU(STOP) | Stop setup time | 4.0 | µs | |||
tTIMEOUT | Error signal detect time | 5 | 20 | ms | ||
tLOW | Clock low period | 20 | µs | |||
tHIGH | Clock high period | 20 | µs |
Threshold setting is 88.85 mV. |
Threshold setting is –177.7 mV. |
Threshold setting is 465 µs. |
This is the VCELL average for single cell. |
Threshold setting is –25 mV. |
Threshold setting is –88.85 mV. |
Threshold setting is 11 ms. |
Threshold setting is 465 µs (including internal delay). |
This is the VCELL average for single cell. |
ISET = 100 mA |
The bq4050 device, incorporating Compensated End-of-Discharge Voltage (CEDV) technology, provides cell balancing while charging or at rest. This fully integrated, single-chip, pack-based solution, including a diagnostic lifetime data monitor and black box recorder, provides a rich array of features for gas gauging, protection, and authentication for 1-series, 2-series, 3-series, and 4-series cell Li-Ion and Li-Polymer battery packs.
The bq4050 gas gauge supports a wide range of battery and system protection features that can easily be configured. See the bq4050 Technical Reference Manual (SLUUAQ3) for detailed descriptions of each protection function.
The primary safety features include:
The secondary safety features of the bq4050 gas gauge can be used to indicate more serious faults via the FUSE pin. This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or discharging. See the bq4050 Technical Reference Manual (SLUUAQ3) for detailed descriptions of each protection function.
The secondary safety features provide protection against:
The bq4050 gas gauge charge control features include:
The bq4050 gas gauge uses the Compensated End-of-Discharge Voltage (CEDV) algorithm to measure and calculate the available capacity in battery cells. The bq4050 device accumulates a measure of charge and discharge currents, estimates self-discharge of the battery, and adjusts the self-discharge estimation based on temperature. See the bq4050 Technical Reference Manual (SLUUAQ3) for further details.
The bq4050 gas gauge fully integrates the system oscillators and does not require any external components to support this feature.
The bq4050 gas gauge checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external system, the bq4050 device detects this as system present.
For battery maintenance, the emergency shutdown feature enables a push button action connecting the SHUTDN pin to shut down an embedded battery pack system before removing the battery. A high-to-low transition of the SHUTDN pin signals the bq4050 gas gauge to turn off the CHG and DSG FETs, disconnecting the power from the system to safely remove the battery pack. The CHG and DSG FETs can be turned on again by another high-to-low transition detected by the SHUTDN pin or when a data flash configurable timeout is reached.
In a 1-series cell configuration, VC4 is shorted to VC, VC2, and VC1. In a 2-series cell configuration, VC4 is shorted to VC3 and VC2. In a 3-series cell configuration, VC4 is shorted to VC3.
The device reduces the charge difference of the battery cells in a fully charged state of the battery pack by gradually using a voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for cell balancing to be active. This prevents fully charged cells from overcharging and causing excessive degradation, and increases the usable pack energy by preventing premature charge termination.
The bq4050 gas gauge uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a second delta-sigma ADC for individual cell and battery voltage and temperature measurement.
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage drop across a small-value sense resistor between the SRP and SRN terminals. The integrating ADC measures bipolar signals from –0.1 V to 0.1 V. The bq4050 gauge detects charge activity when VSR = V(SRP) – V(SRN) is positive, and discharge activity when VSR = V(SRP) – V(SRN) is negative. The bq4050 gas gauge continuously integrates the signal over time, using an internal counter. The fundamental rate of the counter is 0.26 nVh.
Required for WIN8 OS, the battery trip point (BTP) feature indicates when the RSOC of a battery pack has depleted to a certain value set in a DF register. This feature enables a host to program two capacity-based thresholds that govern the triggering of a BTP interrupt on the BTP_INT pin and the setting or clearing of the OperationStatus[BTP_INT] on the basis of RemainingCapacity().
An internal weak pullup is applied when the BTP feature is active. Depending on the system design, an external pullup may be required to put on the BTP_INT pin. See Electrical Characteristics: PRES, BTP_INT, DISP for details.
The bq4050 gas gauge offers lifetime data logging for several critical battery parameters. The following parameters are updated every 10 hours if a difference is detected between values in RAM and data flash:
(This data is updated every 2 hours if a difference is detected.)
(This data is updated every 2 hours if a difference is detected.)
The bq4050 gas gauge supports authentication by the host using SHA-1.
The bq4050 gas gauge can drive a 3-, 4-, or 5- segment LED display for remaining capacity indication and/or a permanent fail (PF) error code indication.
The bq4050 gas gauge updates the individual series cell voltages at 0.25-s intervals. The internal ADC of the bq4050 device measures the voltage, and scales and calibrates it appropriately. This data is also used to calculate the impedance of the cell for the CEDV gas gauging.
The bq4050 gas gauge uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current using a 1-mΩ to 3-mΩ typ. sense resistor.
The bq4050 gas gauge has an internal temperature sensor and inputs for four external temperature sensors. All five temperature sensor options can be individually enabled and configured for cell or FET temperature usage. Two configurable thermistor models are provided to enable monitoring of the cell temperature in addition to the FET temperature, which use a different thermistor profile.
The bq4050 gas gauge uses SMBus v1.1 with MASTER mode and packet error checking (PEC) options per the SBS specification.
The bq4050 gas gauge detects an SMBus off state when SMBC and SMBD are low for two or more seconds. Clearing this state requires that either SMBC or SMBD transition high. The communication bus will resume activity within 1 ms.
See the bq4050 Technical Reference Manual (SLUUAQ3) for further details.
The bq4050 gas gauge supports three power modes to reduce power consumption:
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The bq4050 gas gauge has primary protection support to be used with a 1-series to 4-series Li-Ion/Li Polymer battery pack. To implement and design a comprehensive set of parameters for a specific battery pack, users need the Battery Management Studio (bqStudio) graphical user-interface tool installed on a PC during development. The firmware installed on the bqStudio tool has default values for this product, which are summarized in the bq4050 Technical Reference Manual (SLUUAQ3). Using the bqStudio tool, these default values can be changed to cater to specific application requirements during development once the system parameters, such as fault trigger thresholds for protection, enable/disable of certain features for operation, configuration of cells, chemistry that best matches the cell used, and more are known. This data is referred to as the "golden image."
Table 1 shows the default settings for the main parameters. Use the bqStudio tool to update the settings to meet the specific application or battery pack configuration requirements.
The device should be calibrated before any gauging test. Follow the information in the bqStudio Calibration page to calibrate the device, and use the bqStudio Chemistry page to update the match chemistry profile to the device.
DESIGN PARAMETER | EXAMPLE |
---|---|
Cell Configuration | 3s1p (3-series with 1 Parallel)(1) |
Design Capacity | 4400 mAh |
Device Chemistry | 1210 (LiCoO2/graphitized carbon) |
Cell Overvoltage at Standard Temperature | 4300 mV |
Cell Undervoltage | 2500 mV |
Shutdown Voltage | 2300 mV |
Overcurrent in CHARGE Mode | 6000 mA |
Overcurrent in DISCHARGE Mode | –6000 mA |
Short Circuit in CHARGE Mode | 0.1 V/Rsense across SRP, SRN |
Short Circuit in DISCHARGE Mode | 0.1 V/Rsense across SRP, SRN |
Safety Overvoltage | 4500 mV |
Cell Balancing | Disabled |
Internal and External Temperature Sensor | External Temperature Sensors are used. |
Undertemperature Charging | 0°C |
Undertemperature Discharging | 0°C |
BROADCAST Mode | Disabled |
Battery Trip Point (BTP) with active high interrupt | Disabled |
The high-current path begins at the PACK+ terminal of the battery pack. As charge current travels through the pack, it finds its way through protection FETs, a chemical fuse, the lithium-ion cells and cell connections, and the sense resistor, and then returns to the PACK– terminal (see Figure 22). In addition, some components are placed across the PACK+ and PACK– terminals to reduce effects from electrostatic discharge.
Select the N-CH charge and discharge FETs for a given application. Most portable battery applications are a good match for the CSD17308Q3. The TI CSD17308Q3 is a 47A, 30-V device with Rds(on) of 8.2 mΩ when the gate drive voltage is 8 V.
If a precharge FET is used, R1 is calculated to limit the precharge current to the desired rate. Be sure to account for the power dissipation of the series resistor. The precharge current is limited to (VCHARGER – VBAT)/R1 and maximum power dissipation is (Vcharger – Vbat)2/R1.
The gates of all protection FETs are pulled to the source with a high-value resistor between the gate and source to ensure they are turned off if the gate drive is open.
Capacitors C1 and C2 help protect the FETs during an ESD event. Using two devices ensures normal operation if one becomes shorted. To have good ESD protection, the copper trace inductance of the capacitor leads must be designed to be as short and wide as possible. Ensure that the voltage ratings of C1 and C2 are adequate to hold off the applied voltage if one of the capacitors becomes shorted.
The chemical fuse (Dexerials, Uchihashi, and so on) is ignited under command from either the bq294700 secondary voltage protection IC or from the FUSE pin of the gas gauge. Either of these events applies a positive voltage to the gate of Q5, shown in Figure 23, which then sinks current from the third terminal of the fuse, causing it to ignite and open permanently.
It is important to carefully review the fuse specifications and match the required ignition current to that available from the N-CH FET. Ensure that the proper voltage, current, and Rds(on) ratings are used for this device. The fuse control circuit is discussed in detail in FUSE Circuitry.
The important part to remember about the cell connections is that high current flows through the top and bottom connections; therefore, the voltage sense leads at these points must be made with a Kelvin connection to avoid any errors due to a drop in the high-current copper trace. The location marked 4P in Figure 24 indicates the Kelvin connection of the most positive battery node. The connection marked 1N is equally important. The VC5 pin (a ground reference for cell voltage measurement), which is in the older generation devices, is not in the bq4050 device. Therefore, the single-point connection at 1N to the low-current ground is needed to avoid an undesired voltage drop through long traces while the gas gauge is measuring the bottom cell voltage.
As with the cell connections, the quality of the Kelvin connections at the sense resistor is critical. The sense resistor must have a temperature coefficient no greater than 50 ppm in order to minimize current measurement drift with temperature. Choose the value of the sense resistor to correspond to the available overcurrent and short-circuit ranges of the bq4050 gauge. Select the smallest value possible to minimize the negative voltage generated on the bq4050 VSS node(s) during a short circuit. This pin has an absolute minimum of –0.3 V. Parallel resistors can be used as long as good Kelvin sensing is ensured. The device is designed to support a 1-mΩ to 3-mΩ sense resistor.
The ground scheme of bq4050 gauge is different from the older generation devices. In previous devices, the device ground (or low current ground) is connected to the SRN side of the Rsense resistor pad. The bq4050 gauge, however, it connects the low-current ground on the SRP side of the Rsense resistor pad close to the battery 1N terminal (see Lithium-Ion Cell Connections). This is because the bq4050 gauge has one less VC pin (a ground reference pin VC5) compared to the previous devices. The pin was removed and was internally combined to SRP.
A pair of series 0.1-μF ceramic capacitors is placed across the PACK+ and PACK– terminals to help in the mitigation of external electrostatic discharges. The two devices in series ensure continued operation of the pack if one of the capacitors becomes shorted.
Optionally, a tranzorb such as the SMBJ2A can be placed across the terminals to further improve ESD immunity.
The gas gauge circuit includes the bq4050 gauge and its peripheral components. These components are divided into the following groups: Differential Low-Pass Filter, PBI, system present, SMBus Communication, FUSE circuit, and LED.
The bq4050 gauge uses an integrating delta-sigma ADC for current measurements. Add a 100-Ω resistor from the sense resistor to the SRP and SRN inputs of the device. Place a 0.1-µF (C18) filter capacitor across the SRP and SRN inputs. Optional 0.1-µF filter capacitors (C19 and C20) can be added for additional noise filtering if required for a circuit.
The bq4050 gauge has an internal LDO that is internally compensated and does not require an external decoupling capacitor.
The PBI pin is used as a power supply backup input pin providing power during brief transient power outages. A standard 2.2-µF ceramic capacitor is connected from the PBI pin to ground as shown in Figure 27.
The system present signal is used to inform the gas gauge whether the pack is installed into or removed from the system. In the host system, this pin is grounded. The PRES pin of the bq4050 gauge is occasionally sampled to test for system present. To save power, an internal pullup is provided by the gas gauge during a brief 4-μs sampling pulse once per second. A resistor can be used to pull the signal low and the resistance must be 20 kΩ or lower to ensure that the test pulse is lower than the VIL limit. The pullup current source is typically 10 µA to 20 µA.
Because the system present signal is part of the pack connector interface to the outside world, it must be protected from external electrostatic discharge events. An integrated ESD protection on the PRES device pin reduces the external protection requirement to just R29 for an 8-kV ESD contact rating. However, if it is possible that the system present signal may short to PACK+, then R28 and D4 must be included for high-voltage protection.
The SMBus clock and data pins have integrated high-voltage ESD protection circuits; however, adding a Zener diode (D2 and D3) and series resistor (R24 and R26) provides more robust ESD performance.
The SMBus clock and data lines have internal pulldown. When the gas gauge senses that both lines are low (such as during removal of the pack), the device performs auto-offset calibration and then goes into SLEEP mode to conserve power.
The FUSE pin of the bq4050 gauge is designed to ignite the chemical fuse if one of the various safety criteria is violated. The FUSE pin also monitors the state of the secondary-voltage protection IC. Q5 ignites the chemical fuse when its gate is high. The 7-V output of the bq294700 is divided by R16 and R6, which provides adequate gate drive for Q5 while guarding against excessive back current into the bq294700 if the FUSE signal is high.
Using C3 is generally a good practice, especially for RFI immunity. C3 may be removed, if desired, because the chemical fuse is a comparatively slow device and is not affected by any submicrosecond glitches that come from the FUSE output during the cell connection process.
When the bq4050 gauge is commanded to ignite the chemical fuse, the FUSE pin activates to give a typical 8-V output. The new design makes it possible to use a higher Vgs FET for Q5. This improves the robustness of the system, as well as widens the choices for Q5.
The bq4050 gauge provides secondary overcurrent and short-circuit protection, cell balancing, cell voltage multiplexing, and voltage translation. The following discussion examines cell and battery inputs, pack and FET control, temperature output, and cell balancing.
Each cell input is conditioned with a simple RC filter, which provides ESD protection during cell connect and acts to filter unwanted voltage transients. The resistor value allows some trade-off for cell balancing versus safety protection.
The integrated cell balancing FETs allow the AFE to bypass cell current around a given cell or numerous cells, effectively balancing the entire battery stack. External series resistors placed between the cell connections and the VCx I/O pins set the balancing current magnitude. The internal FETs provide a 200-Ω resistance (2 V < VDS < 4 V). Series input resistors between 100 Ω and 1 kΩ are recommended for effective cell balancing.
The BAT input uses a diode (D1) to isolate and decouple it from the cells in the event of a transient dip in voltage caused by a short-circuit event.
Also, as described in High-Current Path, the top and bottom nodes of the cells must be sensed at the battery connections with a Kelvin connection to prevent voltage sensing errors caused by a drop in the high-current PCB copper.
Internal cell balancing can only support up to 10 mA. External cell balancing is provided as another option for faster cell balancing. For details, refer to the application note, Fast Cell Balancing Using External MOSFET (SLUA420).
The PACK and VCC inputs provide power to the bq4050 gauge from the charger. The PACK input also provides a method to measure and detect the presence of a charger. The PACK input uses a 100-Ω resistor; whereas, the VCC input uses a diode to guard against input transients and prevents misoperation of the date driver during short-circuit events.
The N-CH charge and discharge FETs are controlled with 5.1-kΩ series gate resistors, which provide a switching time constant of a few microseconds. The 10-MΩ resistors ensure that the FETs are off in the event of an open connection to the FET drivers. Q4 is provided to protect the discharge FET (Q3) in the event of a reverse-connected charger. Without Q4, Q3 can be driven into its linear region and suffer severe damage if the PACK+ input becomes slightly negative.
Q4 turns on in that case to protect Q3 by shorting its gate to source. To use the simple ground gate circuit, the FET must have a low gate turn-on threshold. If it is desired to use a more standard device, such as the 2N7002 as the reference schematic, the gate should be biased up to 3.3 V with a high-value resistor. The bq4050 device has the capability to provide a current-limited charging path typically used for low battery voltage or low temperature charging. The bq4050 device uses an external P-channel, precharge FET controlled by PCHG.
For the bq4050 device, TS1, TS2, TS3, and TS4 provide thermistor drive-under program control. Each pin can be enabled with an integrated 18-kΩ (typical) linearization pullup resistor to support the use of a 10-kΩ at 25°C (103) NTC external thermistor, such as a Mitsubishi BN35-3H103. The reference design includes four 10-kΩ thermistors: RT1, RT2, RT3, and RT4. The bq4050 device supports up to four external thermistors. Connect unused thermistor pins to VSS.
Three LED control outputs provide constant current sinks for the driving external LEDs. These outputs are configured to provide voltage and control for up to 5 LEDs. No external bias voltage is required. Unused LEDCNTL pins can remain open or they can be connected to VSS. The DISP pin should be connected to VSS, if the LED feature is not used.
The bq4050 device provides support for a safety PTC thermistor. The PTC thermistor is connected between PTC and PTCEN, and PTCEN is connected to BAT. It can be placed close to the CHG/DSG FETs to monitor the temperature. A PTC fault is one of the permanent failure modes. It can only be cleared by a POR.
To disable, connect PTC and PTCEN to VSS.
Threshold setting is –25 mV. |
Threshold setting is –88.85 mV. |
Threshold setting is 11 ms. |
Threshold setting is 88.85 mV. |
Threshold setting is –177.7 mV. |
Threshold setting is 465 µs. |
The device manages its supply voltage dynamically according to the operation conditions. Normally, the BAT input is the primary power source to the device. The BAT pin should be connected to the positive termination of the battery stack. The input voltage for the BAT pin ranges from 2.2 V to 26 V.
The VCC pin is the secondary power input, which activates when the BAT voltage falls below minimum VCC. This allows the device to source power from a charger (if present) connected to the PACK pin. The VCC pin should be connected to the common drain of the CHG and DSG FETs. The charger input should be connected to the PACK pin.