11.1.1 PCB Layout

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high-frequency current-path loop (see Figure 12) is important to prevent electrical and magnetic field radiation and high-frequency resonant problems. The following is a PCB layout priority list for proper layout. Layout of the PCB according to this specific order is essential.

1. Place the input capacitor as close as possible to the switching MOSFET supply and ground connections and use the shortest possible copper trace connection. The capacitors should be placed on the same layer as the FETs instead of using vias to connect the capacitor and the FETs. Additionally, any vias connecting the input capacitor to the adaptor node should not be placed between the capacitor and the FETs; the capacitor should have a solid copper path to the FET.
2. The IC should be placed close to the switching MOSFET gate pins to keep the gate-drive signal traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB from the switching MOSFETs.
3. Place the inductor input pin as close as possible to the switching MOSFET output pin. Minimize the copper area of this trace to lower electrical and magnetic field radiation, but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
4. The charging-current sensing resistor should be placed right next to the inductor output. Route the sense leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop area) and do not route the sense leads through a high-current path (see Figure 13 for Kelvin connection for best current accuracy). Place the decoupling capacitor on these traces next to the IC.
5. Place the output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor ground before connecting to system ground.
7. Place the sense resistor and filter components, R1, C2, and C3, as close as possible to the IC and directly adjacent to the decoupling capacitor between HSRN and HSRP.
8. Route the analog ground separately from the power ground and use a single ground connection to tie the charger power ground to the charger analog ground. Just beneath the IC, use the copper-pour for analog ground, but avoid power pins to reduce inductive and capacitive noise coupling. Connect analog ground to GND. Connect analog ground and power ground together using the thermal pad as the single ground connection point. Or use a 0-Ω resistor to tie analog ground to power ground (thermal pad should tie to analog ground in this case). A star connection under the thermal pad is highly recommended.
9. It is critical that the exposed thermal pad on the back side of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC connecting to the ground plane on the other layers.
10. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
11. Size and number of all vias should be enough for a given current path.

Figure 12. High-Frequency Current Path

Figure 13. Sensing Resistor PCB Layout

For the recommended component placement with trace and via locations, see the bq40z60EVM SBS 1.1 Impedance Track™ Technology Enabled Battery Management Solution Evaluation Module User's Guide (SLUUB71).

For the QFN information, see the Quad Flatpack No-Lead Logic Packages Application Note (SCBA017) and the QFN/SON PCB Attachment Application Note (SLUA271).