SLUSBV4B June   2018  – September 2020 BQ40Z80

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Primary (1st Level) Safety Features
      2. 8.3.2  Secondary (2nd Level) Safety Features
      3. 8.3.3  Charge Control Features
      4. 8.3.4  Gas Gauging
      5. 8.3.5  Multifunction Pins
      6. 8.3.6  Configuration
        1. 8.3.6.1 Oscillator Function
        2. 8.3.6.2 System Present Operation
        3. 8.3.6.3 Emergency Shutdown
        4. 8.3.6.4 2-Series, 3-Series, 4-Series, 5-Series, or 6-Series Cell Configuration
        5. 8.3.6.5 Cell Balancing
      7. 8.3.7  Battery Parameter Measurements
        1. 8.3.7.1 Charge and Discharge Counting
      8. 8.3.8  Lifetime Data Logging Features
      9. 8.3.9  Authentication
      10. 8.3.10 LED Display
      11. 8.3.11 IATA Support
      12. 8.3.12 Voltage
      13. 8.3.13 Current
      14. 8.3.14 Temperature
      15. 8.3.15 Communications
        1. 8.3.15.1 SMBus On and Off State
        2. 8.3.15.2 SBS Commands
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Using the BQ40Z80EVM with BQSTUDIO
        2. 9.2.2.2 High-Current Path
          1. 9.2.2.2.1 Protection FETs
          2. 9.2.2.2.2 Chemical Fuse
          3. 9.2.2.2.3 Lithium-Ion Cell Connections
          4. 9.2.2.2.4 Sense Resistor
          5. 9.2.2.2.5 ESD Mitigation
        3. 9.2.2.3 Gas Gauge Circuit
          1. 9.2.2.3.1 Coulomb-Counting Interface
          2. 9.2.2.3.2 Power Supply Decoupling and PBI
          3. 9.2.2.3.3 System Present
          4. 9.2.2.3.4 SMBus Communication
          5. 9.2.2.3.5 FUSE Circuitry
        4. 9.2.2.4 Secondary-Current Protection
          1. 9.2.2.4.1 Cell and Battery Inputs
          2. 9.2.2.4.2 External Cell Balancing
          3. 9.2.2.4.3 PACK and FET Control
          4. 9.2.2.4.4 Pre-Discharge Control
          5. 9.2.2.4.5 Temperature Output
          6. 9.2.2.4.6 LEDs
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
      2. 11.1.2 ESD Spark Gap
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.2.2.5 ESD Mitigation

A pair of series 0.1-µF ceramic capacitors is placed across the PACK+ and PACK– terminals to help mitigate external electrostatic discharges. The two devices in series ensure continued operation of the pack if one of the capacitors becomes shorted.

Optionally, a transorb such as the SMBJ2A can be placed across the terminals to further improve ESD immunity.