SLUSFB5 June   2024 BQ41Z50

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Equivalent Diagrams
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Supply Current
    6. 6.6  Power Supply Control
    7. 6.7  Current Wake Detector
    8. 6.8  VC0, VC1, VC2, VC3, VC4, PACK
    9. 6.9  SMBD, SMBC
    10. 6.10 PRES/SHUTDN, DISP
    11. 6.11 ALERT
    12. 6.12 Coulomb Counter Digital Filter (CC1)
    13. 6.13 ADC Digital Filter
    14. 6.14 CHG, DSG High-side NFET Drivers
    15. 6.15 Precharge (PCHG) FET Drive
    16. 6.16 FUSE Drive
    17. 6.17 Internal Temperature Sensor
    18. 6.18 TS1, TS2, TS3, TS4
    19. 6.19 Flash Memory
    20. 6.20 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7
    21. 6.21 Elliptical Curve Cryptography (ECC)
    22. 6.22 SMBus Interface Timing
    23. 6.23 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Primary (1st Level) Safety Features
      2. 7.3.2 Secondary (2nd Level) Safety Features
      3. 7.3.3 Charge Control Features
      4. 7.3.4 Gas Gauging
      5. 7.3.5 Lifetime Data Logging Features
      6. 7.3.6 Authentication
      7. 7.3.7 Configuration
        1. 7.3.7.1 Oscillator Function
        2. 7.3.7.2 Real Time Clock
        3. 7.3.7.3 System Present Operation
        4. 7.3.7.4 Emergency Shutdown
        5. 7.3.7.5 2-Series, 3-Series, or 4-Series Cell Configuration
        6. 7.3.7.6 Cell Balancing
        7. 7.3.7.7 LED Display
      8. 7.3.8 Battery Parameter Measurements
        1. 7.3.8.1 Charge and Discharge Counting
        2. 7.3.8.2 Voltage
        3. 7.3.8.3 Current
        4. 7.3.8.4 Temperature
        5. 7.3.8.5 Communications
          1. 7.3.8.5.1 SMBus On and Off State
    4. 7.4 Device Functional Modes
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 High-Current Path
          1. 8.2.2.1.1 Protection FETs
          2. 8.2.2.1.2 Chemical Fuse
          3. 8.2.2.1.3 Lithium-Ion Cell Connections
          4. 8.2.2.1.4 Sense Resistor
          5. 8.2.2.1.5 ESD Mitigation
        2. 8.2.2.2 Gas Gauge Circuit
          1. 8.2.2.2.1 Coulomb-Counting Interface
          2. 8.2.2.2.2 Low-dropout Regulators (LDOs)
            1. 8.2.2.2.2.1 REG18
            2. 8.2.2.2.2.2 REG135
          3. 8.2.2.2.3 System Present
          4. 8.2.2.2.4 SMBus Communication
          5. 8.2.2.2.5 FUSE Circuitry
        3. 8.2.2.3 Secondary-Current Protection
          1. 8.2.2.3.1 Cell and Battery Inputs
          2. 8.2.2.3.2 External Cell Balancing
          3. 8.2.2.3.3 PACK and FET Control
          4. 8.2.2.3.4 Temperature Measurement
          5. 8.2.2.3.5 LEDs
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
        2. 8.4.1.2 ESD Spark Gap
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.22 SMBus Interface Timing

Typical values stated where TA = 25°C and VBAT = 14.4V, Min/Max values stated where TA = –40°C to 85°C and VBAT = 3.0V to 28V (unless otherwise noted)(1)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SMBus 100kHz
fSMB SMBus operating frequency TARGET mode, SMBC 50% duty cycle 10 100 kHz
fMAS SMBus host clock frequency 10 100 kHz
tBUF Bus free time between start and stop 4.7 µs
tHD:START Hold time after (repeated) start 4 µs
tSU:START Repeated start setup time 4.7 µs
tSU:STOP Stop setup time 4 µs
tHD:DATA Data hold time 0 ns
tSU:DATA Data setup time 250 ns
tTIMEOUT Error signal detect time 25 35 ms
tLOW Clock low period 4.7 µs
tHIGH Clock high period 4 50 µs
tLOW(SEXT) Cumulative clock low target extend time 25 ms
tLOW(MEXT) Cumulative clock low host extend time 10 ms
tF Clock fall time VIH(MIN) + 0.15 to VIL(MAX) – 0.15 300 ns
tR Clock rise time VIL(MAX) – 0.15 to VIH(MIN) + 0.15 1000 ns
tBUSLO Max SMBC/SMBD Low (BUSLO) Signal Detect Time by device BLTx = 0x1 to 0x7 0.5 3.5 s
ΔtBUSLO BUSLO detect time program step 0.5 s
CD Capacitive load for each bus line 400 pF
SMBus 400kHz
fSMB SMBus operating frequency TARGET mode, SMBC 50% duty cycle 10 400 kHz
fMAS SMBus host clock frequency 10 400 kHz
tBUF Bus free time between start and stop 1.3 µs
tHD:START Hold time after (repeated) start 0.6 µs
tSU:START Repeated start setup time 0.6 µs
tSU:STOP Stop setup time 0.6 µs
tHD:DATA Data hold time 0 ns
tSU:DATA Data setup time 100 ns
tTIMEOUT Error signal detect time 25 35 ms
tLOW Clock low period 1.3 µs
tHIGH Clock high period 0.6 50 µs
tLOW(SEXT) Cumulative clock low target extend time 25 ms
tLOW(MEXT) Cumulative clock low host extend time 10 ms
tF Clock fall time VIH(MIN) + 0.15 to VIL(MAX) – 0.15 300 ns
tR Clock rise time VIL(MAX) – 0.15 to VIH(MIN) + 0.15 300 ns
tBUSLO Max SMBC/SMBD Low (BUSLO) Signal Detect Time by device BLTx = 0x1 to 0x7 0.5 3.5 s
ΔtBUSLO BUSLO detect time program step 0.5 s
CD Capacitive load for each bus line 400 pF
SMBus 1MHz
fSMB SMBus operating frequency TARGET mode, SMBC 50% duty cycle 10 1000 kHz
fMAS SMBus host clock frequency 10 1000 kHz
tBUF Bus free time between start and stop 0.5 µs
tHD:START Hold time after (repeated) start 0.26 µs
tSU:START Repeated start setup time 0.26 µs
tSU:STOP Stop setup time 0.26 µs
tHD:DATA Data hold time 0 ns
tSU:DATA Data setup time 50 ns
tTIMEOUT Error signal detect time 25 35 ms
tLOW Clock low period 0.5 µs
tHIGH Clock high period 0.26 50 µs
tLOW(SEXT) Cumulative clock low target extend time 25 ms
tLOW(MEXT) Cumulative clock low host extend time 10 ms
tF Clock fall time VIH(MIN) + 0.15 to VIL(MAX) – 0.15 120 ns
tR Clock rise time VIL(MAX) – 0.15 to VIH(MIN) + 0.15 120 ns
tBUSLO Max SMBC/SMBD Low (BUSLO) Signal Detect Time by device BLTx = 0x1 to 0x7 0.5 3.5 s
ΔtBUSLO BUSLO detect time program step 0.5 s
CD Capacitive load for each bus line 100 pF
(1) Specified by design. Not production tested
BQ41Z50 SMBus Timing Diagram Figure 6-1 SMBus Timing Diagram