SLPS585 March   2016

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Powering bq500101 And Gate Drivers
      2. 7.3.2 Undervoltage Lockout Protection (UVLO)
      3. 7.3.3 Integrated Boost-Switch
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Curves
    3. 8.3 System Example
      1. 8.3.1 Power Loss Curves
      2. 8.3.2 Safe Operating Area (SOA) Curves
      3. 8.3.3 Normalized Curves
        1. 8.3.3.1 Calculating Power Loss and SOA
          1. 8.3.3.1.1 Design Example
          2. 8.3.3.1.2 Calculating Power Loss
          3. 8.3.3.1.3 Calculating SOA Adjustments
  9. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended PCB Design Overview
      2. 9.1.2 Electrical Performance
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Trademarks
    2. 10.2 Electrostatic Discharge Caution
    3. 10.3 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Drawing
    2. 11.2 Recommended PCB Land Pattern
    3. 11.3 Recommended Stencil Opening

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DPC|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The Power Stage bq500101 is a highly optimized design for wireless power transmitter applications using NexFET devices with a 5-V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a rating method is used that is tailored towards a more systems centric environment. The high-performance gate driver device integrated in the package helps minimize the parasitics and results in extremely fast switching of the power MOSFETs. System level performance curves such as Power Loss, Safe Operating Area and normalized graphs allow engineers to predict the product performance in the actual application.

8.2 Typical Application

bq500101 Full.gif Figure 2. Application Schematic

8.2.1 Application Curves

TJ = 125°C, unless stated otherwise
bq500101 D002_SLPS585_r2.gif
VIN = 10 V VDD = 5 V
ƒSW = 130 kHz LSW = 6 µH Duty Cycle = 50%
Figure 3. Power Loss vs Output Current
bq500101 D004_SLPS585_r2.gif
VIN = 10 V VDD = 5 V
ƒSW = 130 kHz LSW = 6 µH Duty Cycle = 50%
Figure 5. Safe Operating Area – PCB Horizontal Mount LFM: Linear Feet per Minute (Air Flow Velocity)
LFM: Linear Feet per Minute (Air Flow Velocity)
bq500101 D007_SLPS585_r2.gif
VIN = 10 V VDD = 5 V
ISW = 5 A LSW = 6 µH Duty Cycle = 50%
Figure 7. Normalized Power Loss vs Frequency
bq500101 D010_SLPS585.gif
VIN = 10 V VDD = 5 V ISW = 5 A
ƒSW = 130 kHz Duty Cycle = 50%
Figure 9. Normalized Power Loss vs Output Inductance
bq500101 D003_SLPS585_r2.gif
VIN = 10 V VDD = 5 V
ƒSW = 130 kHz LSW = 6 µH Duty Cycle = 50%
Figure 4. Power Loss vs Temperature
bq500101 D006_SLPS585_r2.gif
VIN = 10 V VDD = 5 V
ƒSW = 130 kHz LSW = 6 µH Duty Cycle = 50%
Figure 6. Typical Safe Operating Area
bq500101 D008_SLPS585_r3.gif
ISW = 5 A VDD = 5 V
ƒSW = 130 kHz LSW = 6 µH Duty Cycle = 50%
Figure 8. Normalized Power Loss vs Input Voltage
  1. The Typical bq500101 System Characteristic curves are based on measurements made on a PCB design with dimensions of 4.0 inches (W) × 3.5 inches (L) × 0.062 inch (T) and 6 copper layers of 1-oz. copper thickness. See the System Example section for detailed explanation.

8.3 System Example

8.3.1 Power Loss Curves

MOSFET centric parameters such as ON-resistance and gate charges are primarily needed by engineers to estimate the loss generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss performance curves. Figure 3 plots the power loss of the bq500101 as a function of load current. This curve is measured by configuring and running the bq500101 as the circuit shown in Figure 10. The measured power loss is the bq500101 device power loss which consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.

Equation 1. Power Loss = (VIN x IIN) + (VDD x IDD) – (VSW_AVG x IOUT)

The power loss curve in Figure 3 is measured at the maximum recommended junction temperature of
TJ = 125°C under isothermal test conditions.

bq500101 Power_Loss_Test_Circuit_r2.gif Figure 10. Power Loss Test Circuit

8.3.2 Safe Operating Area (SOA) Curves

The SOA curves in the bq500101 datasheet give engineers guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 5 and Figure 6 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1-oz. copper thickness.

8.3.3 Normalized Curves

The normalized curves in the bq500101 data sheet give engineers guidance on the Power Loss and SOA adjustments based on their application specific needs. These curves show how the power loss and SOA boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in power loss and the secondary Y-axis is the change is system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is subtracted from the SOA curve.

8.3.3.1 Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example below). Though the Power Loss and SOA curves in this datasheet are taken for a specific set of test conditions, the following procedure will outline the steps engineers should take to predict product performance for any set of system conditions.

8.3.3.1.1 Design Example

Operating Conditions: Output Current (lSW) = 9 A, Input Voltage (VIN ) = 8 V, Switching Frequency (ƒSW) = 300 kHz, Output Inductor (LSW) = 5 µH, Duty Cycle = 50%.

8.3.3.1.2 Calculating Power Loss

  • Typical Power Loss at 9 A = 1.78 W (Figure 3)
  • Normalized Power Loss for switching frequency ≈ 1.03 (Figure 7)
  • Normalized Power Loss for input voltage ≈ 0.96 (Figure 8)
  • Normalized Power Loss for output inductor ≈ 1.075 (Figure 9)
  • Final calculated Power Loss = 1.78 W × 1.03 × 0.96 × 1.075 ≈ 1.89 W

8.3.3.1.3 Calculating SOA Adjustments

  • SOA adjustment for switching frequency ≈ 0.20°C (Figure 7)
  • SOA adjustment for input voltage ≈ –0.30°C (Figure 8)
  • SOA adjustment for output inductor ≈ 0.60°C (Figure 9)
  • Final calculated SOA adjustment = 0.2 + (–0.3) + 0.6 ≈ 0.5°C

bq500101 D013_SLPS585_r2.png Figure 11. Power Stage bq500101 SOA, TA = 25°C

In the design example above, the estimated power loss of the bq500101 would increase to 1.89 W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 0.5°C. Figure 11 graphically shows how the SOA curve would be adjusted accordingly.

  1. Start by drawing a horizontal line from the application current to the SOA curve.
  2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
  3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 0.5°C. In the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board/ambient temperature.