SLPS585 March 2016
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The bq500101 NexFET™ Power Stage is a highly optimized design for use in wireless power transmitter designs. The bq500101 can also be used for synchronous buck applications.
An external VDD voltage is required to supply the integrated gate driver device and provide the necessary gate drive power for the MOSFETS. A 1-µF 10-V X5R or higher ceramic capacitor is recommended to bypass VDD pin to PGND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap supply to drive the Control FET is generated by connecting a 100-nF 16-V X5R ceramic capacitor CBOOT between BOOT and BOOT_R pins. An optional RBOOT resistor in series with CBOOT can be used to slow down the turn on speed of the Control FET and reduce voltage spikes on the VSW node. A typical 1 Ω to 4.7 Ω value is a compromise between switching loss and VSW spike amplitude.
The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As VVDD rises, both the Control FET and Sync FET gates hold actively low at all times until VVDD reaches the higher UVLO threshold (VUVLO_H)., Then the driver becomes operational and responds to PWM command. If VDD falls below the lower UVLO threshold (VUVLO_L = VUVLO_H – Hysteresis), the device disables the driver and drives the outputs of the Control FET and Sync FET gates actively low. Figure 1 shows this function.
To maintain a BOOT-VSW voltage close to VDD (to get lower conduction losses on the high-side FET), the conventional diode between the VDD pin and the BOOT pin is replaced by a FET which is gated by the DRVL signal.