SLUSCN3A July   2016  – August 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 A11 Coil Specification
      2. 7.3.2 Option Select Pins
      3. 7.3.3 LED Modes
      4. 7.3.4 Foreign Object Detection (FOD) and FOD Calibration
      5. 7.3.5 Shut Down Through External Thermal Sensor or Trigger
      6. 7.3.6 Fault Handling and Indication
      7. 7.3.7 Power Transfer Start Signal
      8. 7.3.8 Power-On Reset
      9. 7.3.9 Trickle Charge and CS100
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Transfer
        1. 7.4.1.1 Dynamic Power Limiting™
        2. 7.4.1.2 Operating Frequency Limiting
      2. 7.4.2 Communication
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Selection
        2. 8.2.2.2 Current Monitoring Requirements
        3. 8.2.2.3 Input Voltage Monitoring
        4. 8.2.2.4 Tank Voltage Monitoring
        5. 8.2.2.5 All Unused Pins
        6. 8.2.2.6 Input Regulation
        7. 8.2.2.7 System Input Power Requirements
        8. 8.2.2.8 LED Modes
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Notes
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RHA Package
40-Pin VQFN
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AVCC 40 — Analog l power supply.
AVSS 36, 39 — Analog ground.
BUZZ 15 O DC buzzer output. A 400-ms DC pulse when charging begins. This could also be connected to an LED through a 1-kΩ resistor.
CLK_IN 21 I CLK_OUT signal from the internal oscillator of the bq50002A Analog Front End.
COMM1 22 I Communication channel 1. Typically generated by the bq50002A Analog Front End.
COMM2 23 I Communication channel 2. Typically generated by the bq50002A Analog Front End.
DRV_EN 37 O Driver enable.
DVCC 32 — Digital power supply.
DVSS 31 — Digital ground.
FLIM 33 I Leave floating to conform to the WPC specification 205-kHz maximum operating frequency. Pull down with a 10-kΩ resistor to limit the maximum frequency to 190 kHz.
FOD_CAL 10 I FOD calibration.
FOD_THR 35 I FOD threshold.
ISENSE 3 I Input current sense.
LED_A 11 O Connect to a LED through a 1-kΩ resistor for status indication. Typically GREEN.
LED_B 12 O Connect to a LED through a 1-kΩ resistor for status indication. Typically RED.
LED_C 14 O Connect to a LED through a 1-kΩ resistor for status indication. Typically ORANGE.
LED_MODE 34 I LED mode selection.
MODE 16 O MODE is an output intended for use by the bq50002A Analog Front End indicating whether adjustments should be made using frequency (when MODE is low) or duty-cycle (when MODE is high).
PWM1 / CLK_OUT 1 O If PWM_CTRL is high, this pin outputs PWM1 signal. If PWM_CTRL is low, this pin outputs clock signal. The rising edge of the clock is used to adjust frequency (MODE low) or duty cycle (MODE high) output of the bq50002A Analog Front End.
PWM_CTRL 38 O PWM_CTRL is an output intended for use by the bq50002A Analog Front End to select whether its PWM outputs are generated internally within the bq50002A itself (PWM_CTRL HIGH), or whether they are simply passed through from external signals (PWM_CTRL LOW).
PWM2 / UP_DOWN 2 O If PWM_CTRL is high, this pin outputs PWM2 signal. If PWM_CTRL is low, this pin is used to adjust the frequency (MODE low) or duty cycle (MODE high) of the external PWM output. If this signal is high, it decrease frequency or increase duty cycle. If this signal is low, it increases frequency or decreases duty cycle output of the bq50002A Analog Front End.
Reserved 4 I Leave this pin open.
Reserved 5 I Unused
Reserved 19 I Reserved. Leave this pin open.
Reserved 20 I/O Reserved. Leave this pin open.
SCL 29 I/O 10-kΩ pull-up resistor to 3-V supply. I2C Clock.
SDA 28 I/O 10-kΩ pull-up resistor to 3-V supply. I2C Data.
TSENSE 13 I Temperature sensing for safety shutdown. Connect to 3 V though 10-kΩ resistor if unused.
Unused 6 I Leave this pin open.
Unused 7 I/O Leave this pin open.
Unused 17, 18, 24, 25, 26, 27 I/O Leave this pin open.
VCORE 30 — Regulated internal core power supply. Connect through 0.4-µF capacitor to ground.
VPEAK 8 I Peak coil voltage.
VSENSE 9 I Input voltage sense.