SLUSBX7C September   2014  – March 2017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Dynamic Rectifier Control
      2. 8.3.2  Dynamic Power Scaling
      3. 8.3.3  VO_REG Calculations
      4. 8.3.4  RILIM Calculations
      5. 8.3.5  Adapter Enable Functionality
      6. 8.3.6  Turning Off the Transmitter
        1. 8.3.6.1 WPC v1.2 EPT
      7. 8.3.7  Communication Current Limit
      8. 8.3.8  PD_DET and TMEM
      9. 8.3.9  TS/CTRL
      10. 8.3.10 PMODE Pin
      11. 8.3.11 I2C Communication
      12. 8.3.12 Input Overvoltage
      13. 8.3.13 Alignment Aid Using Frequency Information
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
      1. 8.5.1  Wireless Power Supply Current Register 1
      2. 8.5.2  Wireless Power Supply Current Register 2
      3. 8.5.3  Wireless Power Supply Current Register 3
      4. 8.5.4  I2C Mailbox Register
      5. 8.5.5  I2C Mailbox Register 2
      6. 8.5.6  I2C Mailbox Register 3
      7. 8.5.7  Wireless Power Supply FOD RAM
      8. 8.5.8  Wireless Power User Header RAM
      9. 8.5.9  Wireless Power USER VRECT Status RAM
      10. 8.5.10 Wireless Power VOUT Status RAM
      11. 8.5.11 Wireless Power Proprietary Mode REC PWR MSByte Status RAM
      12. 8.5.12 Wireless Power REC PWR LSByte Status RAM
      13. 8.5.13 Wireless Power Prop Packet Payload RAM Byte 0
      14. 8.5.14 Wireless Power Prop Packet Payload RAM Byte 1
      15. 8.5.15 Wireless Power Prop Packet Payload RAM Byte 2
      16. 8.5.16 Wireless Power Prop Packet Payload RAM Byte 3
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 WPC v1.2 Power Supply 7-V Output With 1.4-A Maximum Current With I2C
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Voltage Set Point
          2. 9.2.1.2.2 Output and Rectifier Capacitors
          3. 9.2.1.2.3 TMEM
          4. 9.2.1.2.4 Maximum Output Current Set Point
          5. 9.2.1.2.5 I2C
          6. 9.2.1.2.6 Communication Current Limit
          7. 9.2.1.2.7 Receiver Coil
          8. 9.2.1.2.8 Series and Parallel Resonant Capacitors
          9. 9.2.1.2.9 Communication, Boot, and Clamp Capacitors
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Standalone 10-V WPC v1.2 Power Supply With 1-A Maximum Output Current in System Board
      3. 9.2.3 Standalone 10-V Power Supply With 1-A Maximum Output Current for 2S Charging System
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1  Output Voltage Set Point
          2. 9.2.3.2.2  Output and Rectifier Capacitors
          3. 9.2.3.2.3  TMEM
          4. 9.2.3.2.4  Maximum Output Current Set Point
          5. 9.2.3.2.5  I2C
          6. 9.2.3.2.6  Communication Current Limit
          7. 9.2.3.2.7  Receiver Coil
          8. 9.2.3.2.8  Series Resonant Capacitors
            1. 9.2.3.2.8.1 Tuning Procedure
          9. 9.2.3.2.9  Communication, Boot, and Clamp Capacitors
          10. 9.2.3.2.10 VRECT Clamp
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

  • Keep the trace resistance as low as possible on AC1, AC2, and OUT.
  • Detection and resonant capacitors need to be as close to the device as possible.
  • COMM, CLAMP, and BOOT capacitors need to be placed as close to the device as possible.
  • Via interconnect on GND net is critical for appropriate signal integrity and proper thermal performance.
  • High-frequency bypass capacitors need to be placed close to RECT and OUT pins.
  • ILIM and FOD resistors are important signal paths and the loops in those paths to GND must be minimized.

    • Signal and sensing traces are the most sensitive to noise; the sensing signal amplitudes are usually measured in mV, which is comparable to the noise amplitude. Make sure that these traces are not being interfered by the noisy and power traces. AC1, AC2, BOOT1, BOOT2, COMM1, and COMM2 are the main source of noise in the board. These traces should be shielded from other components in the board. It is usually preferred to have a ground copper area placed underneath these traces to provide additional shielding. Also, make sure they do not interfere with the signal and sensing traces. The PCB should have a ground plane (return) connected directly to the return of all components through vias (two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components.

    For a 1.4-A fast-charge current application, the current rating for each net is as follows:

    • AC1 = AC2 = 2.2 A
    • OUT = 2.5 A
    • RECT = 200 mA (RMS)
    • COMMx = 600 mA
    • CLAMPx = 1000 mA
    • All others can be rated for 10 mA or less.

11.2 Layout Example

bq51025 layout_SLUSBS9.gif Figure 40. Layout Recommendation