bq5105xB High-Efficiency Qi v1.2-Compliant Wireless Power Receiver and Battery Charger

8.3.4.1 Precharge Mode (V_BAT ≤ V_LOWV)

The bq5105X enters precharge mode when V_BAT ≤ V_LOWV. Upon entering precharge mode, battery charge current limit is set to I_PRECHG. During precharge mode, the charge current is   regulated to K_PRECHG percent of the fast charge current (I_BULK) setting. For example, if IBULK is set to 800 mA, then the precharge current would have a typical value of 160 mA.

If the battery is deeply discharged or shorted (V_BAT < V_BAT(SC)), the bq5105X applies I_BAT(SC) current to bring the battery voltage up to acceptable charging levels. Once the battery rises above V_BAT(SC), the charge current is regulated to I_PRECHG.

Under normal conditions, the time spent in this precharge region is a very short percentage of the total charging time and this does not affect the overall charging efficiency for very long.

8.3.4.2 Fast Charge Mode / Constant Voltage Mode

Once V_BAT > V_LOWV, the bq5105x enters fast charge mode (Current Regulation Phase) where charge current is regulated using the internal MOSFETs between RECT and BAT. Once the battery voltage charges up to V_BAT-REG, the bq5105x enters constant voltage (CV) phase and regulates battery voltage to V_OREG and the charging current is reduced.

Once I_BAT falls below the termination threshold (I_TERM-Th), the charger sends an EPT (Charge Complete) notification to the TX and enters high impedance mode.

8.3.4.3 Battery Charge Current Setting Calculations

8.3.4.3.1 R_ILIM Calculations

The bq5105x includes a means of providing hardware overcurrent protection by means of an analog current regulation loop. The hardware current limit provides an extra level of safety by clamping the maximum allowable output current (for example, a current compliance). The calculation for the total R_ILIM resistance is as follows:

Equation 1.

Where I_BULK is the programmed battery charge current during fast charge mode. When referring to the application diagram shown in Figure 32, R_ILIM is the sum of R_FOD and R₁ (the total resistance from the ILIM pin to PGND).

8.3.4.3.2 Termination Calculations

The bq5105X includes a programmable upper termination threshold. The upper termination threshold is calculated using Equation 2:

Equation 2.

The K_TERM constant is specified in Electrical Characteristics as 240 Ω/%. The upper termination threshold is set as a percentage of the charge current setting (I_BULK).

For example, if R_ILIM is set to 314 Ω, I_BULK will be 1 A (314 ÷ 314). If the upper termination threshold is desired to be 100 mA, this would be 10% of I_BULK. The R_TERM resistor would then equal 2.4 kΩ (240 × 10).

Termination can be disabled by floating the TERM pin. If the TERM pin is grounded the termination function is effectively disabled. However, due to offsets of internal comparators, termination may occur at low battery currents.

8.3.4.4 Battery-Charger Safety and JEITA Guidelines

The bq5105x continuously monitors battery temperature by measuring the voltage between the TS/CTRL pin and PGND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this voltage. The bq5105x compares this voltage against its internal thresholds to determine if charging is allowed. To initiate a charge cycle, the voltage on TS/CTRL pin (V_TS) must be within the V_T1 to V_T4 thresholds. If V_TS is outside of this range, the bq5105x suspends charge and waits until the battery temperature is within the V_T1 to V_T4 range. Additional information on the Temperature Sense function can be found in Internal Temperature Sense (TS Function of the TS/CTRL Pin).

8.3.4.4.1 bq51050B and bq51051B JEITA

If V_TS is within the ranges of V_T1 and V_T2 or V_T3 and V_T4, the charge current is reduced to I_BULK/2. If V_TS is within the range of V_T1 and V_T3, the maximum charge voltage regulation is V_OREG. If V_TS is within the range of V_T3 and V_T4, the maximum charge voltage regulation is reduced to "NEW SPEC". Figure 25 summarizes the operation.

Figure 25. JEITA Compatible TS Profile for bq51050B and bq51051B

8.3.4.4.2 bq51052B Modified JEITA

The bq51052B has a modififed JEITA profile. The maximum charge current is not modified between V_T1 and V_T2 or between V_T3 and V_T4, it remains at I_BULK. The maximum charge voltage is reduced to V_O-J when the V_TS is between V_T3 and V_T4.

Figure 26. JEITA Compatible TS Profile for bq51052B

8.3.4.5 Input Overvoltage

If, for some condition (for example, a change in position of the equipment on the charging pad), the rectifier voltage suddenly increases in potential, the voltage-control loop inside the bq5105x becomes active, and prevents the output from going beyond V_BAT-REG. The receiver then starts sending back error packets every 32 ms until the RECT voltage comes back to an acceptable level, and then maintains the error communication every 250 ms.

If the input voltage increases in potential beyond V_OVP, the device switches off the internal FET and communicates to the primary to bring the voltage back to V_RECT-REG. In addition a proprietary voltage protection circuit is activated by means of C_CLAMP1 and C_CLAMP2 that protects the device from voltages beyond the maximum rating.

8.3.4.6 End Power Transfer Packet (WPC Header 0x02)

The WPC allows for a special command to terminate power transfer from the TX termed End Power Transfer (EPT) packet. WPC v1.2 specifies the reasons for sending a termination packet and their data field value. In Table 1, the CONDITION column corresponds to the stimulus causing the bq5105x device to send the hexidecimal code in the VALUE column.

8.3.4.7 Status Output

The bq5105x provides one status output, CHG. This output is an open-drain NMOS device that is rated to 20 V. The open-drain FET connected to the CHG pin will be turned on whenever the output (BAT) of the charger is enabled. As a note, the output of the charger supply will not be enabled if the V_RECT-REG does not converge to the no-load target voltage.

8.3.4.8 Communication Modulator

The bq5105x provides two identical, integrated communication FETs which are connected to the pins COMM1 and COMM2. These FETs are used for modulating the secondary load current which allows bq5105x to communicate error control and configuration information to the transmitter.There are two methods to implement load modulation, capacitive and resistive.

Capacitive load modulation is more commonly used. Capacitive load modulation is shown in Figure 27. In this case, a capacitor is connected from COMM1 to AC1 and from COMM2 to AC2. When the COMM switches are closed there is effectively a 22 nF capacitor connected between AC1 and AC2. Connecting a capacitor in between AC1 and AC2 modulates the impedance seen by the coil, which will be reflected to the primary and interpreted by the controller as a change in current.

Figure 27. Capacitive Load Modulation

Figure 28 shows how the COMM pins can be used for resistive load modulation. Each COMM pin can handle at most a 24 Ω communication resistor. Therefore, if a COMM resistor between 12 Ω and 24 Ω is required, COMM1 and COMM2 pins must be connected in parallel. bq5105x does not support a COMM resistor less than 12 Ω.

Figure 28. Resistive Load Modulation

8.3.4.9 Adaptive Communication Limit

The Qi communication channel is established through backscatter modulation as described in the previous sections. This type of modulation takes advantage of the loosely coupled inductor relationship between the RX and TX coils. Essentially, the switching in-and-out of the communication capacitor or resistor adds a transient load to the RX coil in order to modulate the TX coil voltage and current waveform (amplitude modulation). The consequence of this technique is that a load transient (load current noise) from the mobile device has the same signature. To provide noise immunity to the communication channel, the output load transients must be isolated from the RX coil. The proprietary feature Adaptive Communication Limit achieves this by dynamically adjusting the current limit of the regulator.

This can be seen in Figure 12. In this plot, an output load is limited to 400 mA during communications time. The pulses on V_RECT indicate that a communication packet event is occurring. The regulator limits the load to a constant 400 mA and, therefore, preserves communication.

8.3.4.10 Synchronous Rectification

The bq5105x provides an integrated, self-driven synchronous rectifier that enables high-efficiency AC to DC power conversion. The rectifier consists of an all NMOS H-Bridge driver where the back gates of the diodes are configured to be the rectifier when the synchronous rectifier is disabled. During the initial start-up of the WPC system the synchronous rectifier is not enabled. At this operating point, the DC rectifier voltage is provided by the diode rectifier. Once V_RECT is greater than V_UVLO, half synchronous mode will be enabled until the load current surpasses I_BAT-SR. Above I_BAT-SR the full synchronous rectifier stays enabled until the load current drops back below the hysteresis level (I_BAT-SRH) where half synchronous mode is re-enabled.

8.3.4.11 Internal Temperature Sense (TS Function of the TS/CTRL Pin)

The bq5105x includes a ratiometric battery temperature sense circuit. The temperature sense circuit has two ratiometric thresholds which represent hot and cold conditions. An external temperature sensor is recommended to provide safe operating conditions to the receiver product. This pin is best used when monitoring the battery temperature.

The circuits in Figure 29 allow for any NTC resistor to be used with the given V_HOT and V_COLD thresholds. The thermister characteristics and threshold temperatures selected will determine which circuit is best for an application.

Figure 29. NTC Circuit Options for Safe Operation of the Wireless Receiver Power Supply

The resistors R1 and R3 can be solved by resolving the system of equations at the desired temperature thresholds. The two equations are:

Equation 3.

Equation 4.

Where:

T_COLD and T_HOT are the desired temperature thresholds in degrees Kelvin. R_o is the nominal resistance at T₀ (25°C) and β is the temperature coefficient of the NTC resistor. For an example solution for part number ERT-JZEG103JA see the BQ5105XB NTC Calculator Tool, (SLUS629).

Where,

T_COLD = 0°C (273.15°K)
T_HOT = 60°C (333.15°K)
β = 3380
R_o = 10 kΩ

The plot of the percent V_TSB versus temperature is shown in Figure 30:

Figure 30. Example Solution for Panasonic Part # ERT-JZEG103JA

Figure 31 shows the periodic biasing scheme used for measuring the TS state. An internal TS_READ signal enables the TS bias voltage for 25 ms. During this period the TS comparators are read (each comparator has a 10-ms deglitch) and appropriate action is taken based on the temperature measurement. After this 25-ms period has elapsed the TS_READ signal goes low, which causes the TS/CTRL pin to become high impedance. During the next 100-ms period, the TS voltage is monitored and compared to V_CTRL-HI. If the TS voltage is greater than V_CTRL-HI then a secondary device is driving the TS/CTRL pin and a CTRL = 1 is detected.

Figure 31. Timing Diagram for TS Detection Circuit

When an NTC resistor is connected between the TS/CTRL pin and PGND, the NTC function is allowed to operate. This functionality can effectively be disabled by connecting a 10 kΩ resistor from TS/CRTL to PGND. If  the TS/CTRL pin is pulled above V_CTRL-HI, the RX is shut down with the indication of a charge complete condition. If the TS/CTRL pin is pulled below V_CTRL-LOW, the RX is shut down with the indication of a fault.

8.3.4.12 WPC v1.2 Compatibility

The bq5105x is a WPC v1.2 compatible device. In order to enable a Power Transmitter to monitor the power loss across the interface as one of the possible methods to limit the temperature rise of Foreign Objects, the bq5105x reports its Received Power to the Power Transmitter. The Received Power equals the power that is available from the output of the Power Receiver plus any power that is lost in producing that output power. For example, the power loss includes (but is not limited to) the power loss in the Secondary Coil and series resonant capacitor, the power loss in the Shielding of the Power Receiver, the power loss in the rectifier, the power loss in any post-regulation stage, and the eddy current loss in metal components or contacts within the Power Receiver. In the WPC v1.2 specification, foreign object detection (FOD) is enforced, that means the bq5105x will send received power information with known accuracy to the transmitter.

WPC v1.2 defines Received Power as “the average amount of power that the Power Receiver receives through its Interface Surface, in the time window indicated in the Configuration Packet”.

A Receiver will be certified as WPC v1.2 only after meeting the following requirement. The device under test (DUT) is tested on a Reference Transmitter whose transmitted power is calibrated, the receiver must send a received power such that:

This 250 mW bias ensures that system will remain interoperable.

WPC v1.2 Transmitters will be tested to see if they can detect reference Foreign Objects with a Reference receiver. The WPC v1.2 specification allows much more accurate sensing of Foreign Objects than WPC v1.0.

A Transmitter can be certified as a WPC v1.2 only after meeting the following requirement. A Transmitter is tested to see if it can prevent some reference Foreign Objects (disc, coin, foil) from exceeding their threshold temperature (60°C, 80°C).

9.2.1.1 Design Requirements

This application is for a 4.2-V Lithium-Ion battery to be charged at 800 mA. Because this is planned for a WPC v1.2 solution, any of the Qi-certified transmitters can be used interchangeably so no discussion of the TX is required. To charge a 4.20-V Li-Ion battery, the bq51050B will be chosen. Each of the components from the application drawing will be examined. Temperature sensing of the battery must be done with JEITA specifications. An LED indicator is required to notify the user if charging is active.

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Series and Parallel Resonant Capacitor Selection

Shown in Figure 33, the capacitors C1 (series) and C2 (parallel) make up the dual resonant circuit with the receiver coil. These two capacitors must be sized correctly per the WPC v1.2 specification. Figure 33 shows the equivalent circuit of the dual resonant circuit:

Figure 33. Dual Resonant Circuit with the Receiver Coil

The power receiver design requirements in volume 1 of the WPC v1.2 specification highlights in detail the sizing requirements. To summarize, the receiver designer will be required take inductance measurements with a fixed test fixture. The test fixture is shown in Figure 34:

Figure 34. WPC v1.2 Receiver Coil Test Fixture for the Inductance Measurement Ls’

The primary shield is to be 50 mm × 50 mm × 1 mm of Ferrite material PC44 from TDK Corp. The gap (dZ) is to be 3.4 mm. The receiver coil, as it will be placed in the final system (for example, the back cover and battery must be included if the system calls for this), is to be placed on top of this surface and the inductance is to be measured at 1-V RMS and a frequency of 100 kHz. This measurement is termed Ls’. The measurement termed Ls is the free-space inductance. Each capacitor can then be calculated using Equation 6:

Equation 6.

Where f_S is 100 kHz +5/–10% and f_D is 1 MHz ±10%. C₁ must be chosen first prior to calculating C₂. The quality factor must be greater than 77 and can be determined by Equation 7:

Equation 7.

Where R is the DC resistance of the receiver coil. All other constants are defined above.

For this application, we will design with an inductance measurement (L) of 11 µH and an Ls' of 16 µH with a DC resistance of 191 mΩ. Plugging Ls' into Equation 6 above, we get a value for C₁ to be 158.3 nF. The range on the capacitance is about 144 nF to 175 nF. To build the resulting value, the optimum solution is usually found with 3 capacitors in parallel. This allows for more precise selection of values, lower effective resistance and better thermal results. To get 158 nF, choose from standard values. In this case, the values are 68 nF, 47 nF and 39 nF for a total of 154 nF. Well in the required range. Now that C₁ is chosen, the value of C₂ can be calculated. The result of this calculation is 2.3 nF. The practical solution for this is 2 capacitors, a 2.2 nF capacitor and a 100 pF capacitor. In all cases, these capacitors must have at least a 25-V rating. Solving for the quality factor (Q) this solution shows a rating over 500.

9.2.1.3 Application Curves

Figure 35. Battery Insertion During Precharge

Figure 36. Precharge to Fast-Charge Transition

9.2.2.1 Design Requirements

The requirements for this solution are identical to the first application so all common components are identical. This solution adds a wired charger and a blocking back-back FET (Q1).

The addition of a wired charger is simply enabled. The AD pin on the bq5105x is tied to the input of the DC supply. When the bq5105x senses a voltage greater than V_AD-Pres on the AD pin, the BAT pin will be disabled (high impedance). Once the BAT pin is disabled, the AD_EN pin will transition and enable Q1. If wireless power is not present, the functionality of AD and AD_EN remains and wired charging can take place.

9.2.2.2 Detailed Design Procedure