SLUSCL5A
July 2016 – August 2016
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Dynamic Rectifier Control
8.3.2
Dynamic Power Scaling
8.3.3
VO_REG and VIREG Calculations
8.3.4
RILIM Calculations
8.3.5
Adapter Enable Functionality
8.3.6
Turning Off the Transmitter
8.3.6.1
WPC End Power Transfer (EPT)
8.3.6.2
PMA EOC
8.3.7
CM_ILIM
8.3.8
PD_DET and TMEM
8.3.9
TS, Both WPC and PMA
8.3.10
I2C Communication
8.3.11
Input Overvoltage
8.4
Device Functional Modes
8.5
Register Maps
8.5.1
Wireless Power Supply Current Register 1 (address = 0x01) [reset = 00000001]
8.5.2
Wireless Power Supply Current Register 2 (address = 0x02) [reset = 00000111 ]
8.5.3
I2C Mailbox Register (address = 0xE0) [reset = 10000000 ]
8.5.4
Wireless Power Supply FOD RAM Register (address = 0xE1) [reset =00000000 ]
8.5.5
Wireless Power User Header RAM Register (address = 0xE2) [reset = 00000000]
8.5.6
Wireless Power USER VRECT Status RAM Register (address = 0xE3) [reset = 00000000]
8.5.7
Wireless Power VOUT Status RAM Register (address = 0xE4) [reset = 00000000]
8.5.8
Wireless Power REC PWR Byte Status RAM Register (address = 0xE8) [reset = 00000000]
8.5.9
Wireless Power Mode Indicator Register (address = 0xEF) [reset = 00000000]
8.5.10
Wireless Power Prop Packet Payload RAM Byte 0 Register (address = 0xF1) [reset = 00000000]
8.5.11
Wireless Power Prop Packet Payload RAM Byte 1 Register (address = 0xF2) [reset = 00000000]
8.5.12
Wireless Power Prop Packet Payload RAM Byte 2 Register (address = 0xF3) [reset = 00000000]
8.5.13
Wireless Power Prop Packet Payload RAM Byte 3 Register (address = 0xF4) [reset = 00000000]
8.5.14
RXID Readback Register (address = 0xF5 - 0xFA) [reset = see note]
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Dual Mode Design (WPC and PMA Compliant) Power Supply 5-V Output with 1-A Maximum Current
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Output Voltage Set Point
9.2.1.2.2
Output and Rectifier Capacitors
9.2.1.2.2.1
TMEM
9.2.1.2.3
Maximum Output Current Set Point
9.2.1.2.4
TERM Resistor
9.2.1.2.5
Setting LPRB1 and LPRB2 Resistors
9.2.1.2.6
I2C
9.2.1.2.7
Communication Current Limit
9.2.1.2.8
Receiver Coil
9.2.1.2.9
Series and Parallel Resonant Capacitors
9.2.1.2.10
Communication, Boot and Clamp Capacitors
9.2.1.3
Application Curves
9.2.2
Embedded in System Board
9.2.3
bq51222 Implemented in Back Cover
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Third-Party Products Disclaimer
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
YFP|42
MXBG339A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sluscl5a_oa
sluscl5a_pm
4 Revision History
Changes from * Revision (July 2016) to A Revision
Changed from Product Preview to Production Data
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