SLUSDT5 Data sheet

SLUSDT5B September 2019 – October 2023 BQ75614-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

PAP|64
- MPQF071C

Thermal pad, mechanical data (Package|Pins)

PAP|64
- PPTD012N

Orderable Information

8.3.6.2.1 Fault Status Hierarchy

The device monitors multiple types of faults such as:

Battery cell monitoring through the hardware protector, like cell OV/UV, cell OT/UT, and so on
System operation driven like device reset, communication timeout, thermal warning, and so on
Command-based diagnostic check related like the various comparison through the main and AUX ADCs, BIST run, and so on
Automatic diagnostic check running in the background like the internal power supplies, OTP CRC, and so on
Communication fault.

Each bit in the FAULT_SUMMARY register represents a group of faults which are stored in one or more lower level fault registers. The FAULT_SUMMARY register represents the highest hierarchy level of fault status detected by the device. Host system can periodically poll the FAULT_SUMMARY register to check the fault status and only read the lower level fault registers if needed (for example, if FAULT_SUMMARY[FAULT_OVUV] = 1, host can read FAULT_OV1/2 and FAULT_UV1/2 registers to determine which cell channel triggered the fault).

Table 8-17 shows which lower level register corresponds to the FAULT_SUMMARY register bit. The description of the register is covered in Section 8.5.

Table 8-17 Low-Level Fault Registers

FAULT_SUMMARY Bit Name	FAULT_PROT	FAULT_COMP_ADC	FAULT_OTP	FAULT_COMM	FAULT_OTUT	FAULT_OVUV	FAULT_SYS	FAULT_PWR
Lower level register name	FAULT_PROT1	FAULT_COMP_GPIO	FAULT_OTP⁽¹⁾	FAULT_ COMM1⁽¹⁾	FAULT_OT	FAULT_OV1	FAULT_SYS	FAULT_PWR1
	FAULT_PROT2	FAULT_COMP_VCCB1			FAULT_UT	FAULT_OV2		FAULT_PWR2
		FAULT_COMP_VCCB2				FAULT_UV1		FAULT_PWR3
		FAULT_COMP_VCOW1				FAULT_UV2
		FAULT_COMP_VCOW2
		FAULT_COMP_CBOW1
		FAULT_COMP_CBOW2
		FAULT_COMP_CBFET1
		FAULT_COMP_CBFET2
		FAULT_COMP_MISC

(1) Some of the bits in the FAULT_COMM1/2 and FAULT_OTP registers have a lower level of fault information than shown in the DEBUG_COMM* and DEBUG_OTP registers.