SLUSE91B September   2020  – January 2022 BQ769142

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information BQ769142
    5. 7.5  Supply Current
    6. 7.6  Digital I/O
    7. 7.7  LD Pin
    8. 7.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 7.9  FUSE Pin Functionality
    10. 7.10 REG18 LDO
    11. 7.11 REG0 Pre-regulator
    12. 7.12 REG1 LDO
    13. 7.13 REG2 LDO
    14. 7.14 Voltage References
    15. 7.15 Coulomb Counter
    16. 7.16 Coulomb Counter Digital Filter (CC1)
    17. 7.17 Current Measurement Digital Filter (CC2)
    18. 7.18 Current Wake Detector
    19. 7.19 Analog-to-Digital Converter
    20. 7.20 Cell Balancing
    21. 7.21 Cell Open Wire Detector
    22. 7.22 Internal Temperature Sensor
    23. 7.23 Thermistor Measurement
    24. 7.24 Internal Oscillators
    25. 7.25 High-side NFET Drivers
    26. 7.26 Comparator-Based Protection Subsystem
    27. 7.27 Timing Requirements - I2C Interface, 100kHz Mode
    28. 7.28 Timing Requirements - I2C Interface, 400kHz Mode
    29. 7.29 Timing Requirements - HDQ Interface
    30. 7.30 Timing Requirements - SPI Interface
    31. 7.31 Interface Timing Diagrams
    32. 7.32 Typical Characteristics
  8. 8 Device Description
    1. 8.1 Overview
    2. 8.2 BQ769142 Device Versions
    3. 8.3 Functional Block Diagram
    4. 8.4 Diagnostics
  9. 9 Device Configuration
    1. 9.1 Commands and Subcommands
    2. 9.2 Configuration Using OTP or Registers
    3. 9.3 Device Security
    4. 9.4 Scratchpad Memory
  10. 10Measurement Subsystem
    1. 10.1  Voltage Measurement
      1. 10.1.1 Voltage Measurement Schedule
      2. 10.1.2 Using VC Pins for Cells Versus Interconnect
      3. 10.1.3 Cell 1 Voltage Validation During SLEEP Mode
    2. 10.2  General Purpose ADCIN Functionality
    3. 10.3  Coulomb Counter and Digital Filters
    4. 10.4  Synchronized Voltage and Current Measurement
    5. 10.5  Internal Temperature Measurement
    6. 10.6  Thermistor Temperature Measurement
    7. 10.7  Factory Trim of Voltage ADC
    8. 10.8  Voltage Calibration (ADC Measurements)
    9. 10.9  Voltage Calibration (COV and CUV Protections)
    10. 10.10 Current Calibration
    11. 10.11 Temperature Calibration
  11. 11Primary and Secondary Protection Subsystems
    1. 11.1 Protections Overview
    2. 11.2 Primary Protections
    3. 11.3 Secondary Protections
    4. 11.4 High-Side NFET Drivers
    5. 11.5 Protection FETs Configuration and Control
      1. 11.5.1 FET Configuration
      2. 11.5.2 PRECHARGE and PREDISCHARGE Modes
    6. 11.6 Load Detect Functionality
  12. 12Device Hardware Features
    1. 12.1  Voltage References
    2. 12.2  ADC Multiplexer
    3. 12.3  LDOs
      1. 12.3.1 Preregulator Control
      2. 12.3.2 REG1 and REG2 LDO Controls
    4. 12.4  Standalone Versus Host Interface
    5. 12.5  Multifunction Pin Controls
    6. 12.6  RST_SHUT Pin Operation
    7. 12.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
    8. 12.8  ALERT Pin Operation
    9. 12.9  DDSG and DCHG Pin Operation
    10. 12.10 Fuse Drive
    11. 12.11 Cell Open Wire
    12. 12.12 Low Frequency Oscillator
    13. 12.13 High Frequency Oscillator
  13. 13Device Functional Modes
    1. 13.1 Overview
    2. 13.2 NORMAL Mode
    3. 13.3 SLEEP Mode
    4. 13.4 DEEPSLEEP Mode
    5. 13.5 SHUTDOWN Mode
    6. 13.6 CONFIG_UPDATE Mode
  14. 14Serial Communications Interface
    1. 14.1 Serial Communications Overview
    2. 14.2 I2C Communications
    3. 14.3 SPI Communications
      1. 14.3.1 SPI Protocol
    4. 14.4 HDQ Communications
  15. 15Cell Balancing
    1. 15.1 Cell Balancing Overview
  16. 16Application and Implementation
    1. 16.1 Application Information
    2. 16.2 Typical Applications
      1. 16.2.1 Design Requirements (Example)
      2. 16.2.2 Detailed Design Procedure
      3. 16.2.3 Application Performance Plot
      4. 16.2.4 Calibration Process
    3. 16.3 Random Cell Connection Support
    4. 16.4 Startup Timing
    5. 16.5 FET Driver Turn-Off
    6. 16.6 Unused Pins
  17. 17Power Supply Requirements
  18. 18Layout
    1. 18.1 Layout Guidelines
    2. 18.2 Layout Example
  19. 19Device and Documentation Support
    1. 19.1 Third-Party Products Disclaimer
    2. 19.2 Documentation Support
    3. 19.3 Support Resources
    4. 19.4 Trademarks
    5. 19.5 Electrostatic Discharge Caution
    6. 19.6 Glossary
  20. 20Mechanical, Packaging, Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.4 High-Side NFET Drivers

The BQ769142 device includes an integrated charge pump and high-side NFET drivers for driving CHG and DSG protection FETs. The charge pump uses an external capacitor connected between the BAT and CP1 pins that is charged to an overdrive voltage when the charge pump is enabled. Due to the time required for the charge pump to bring the overdrive voltage on the external CP1 pin to full voltage, it is recommended to leave the charge pump powered whenever it may be needed quickly to drive the CHG or DSG FETs.

The DSG FET driver includes a special option (denoted source follower mode) to drive the DSG FET with the BAT pin voltage during SLEEP mode. This capability is included to provide low power in SLEEP mode, when there is no significant charge or discharge current flowing. It is recommended to keep the charge pump enabled even when the source follower mode is enabled, so whenever a discharge current is detected, the device can quickly transition to driving the DSG FET using the charge pump voltage. The source follower mode is enabled using a configuration setting and is not intended to be used when significant charging or discharging current is flowing, since the FET will exhibit a large drain-source voltage and may undergo excessive heating.

The overdrive level of the charge pump voltage can be set to 5.5 V or 11 V, based on the configuration setting. In general, the 5.5-V setting results in lower power dissipation when a FET is being driven, while the higher 11-V overdrive reduces the on-resistance of the FET. If a FET exhibits significant gate leakage current when driven at the higher overdrive level, this can result in a higher device current for the charge pump to support this. In this case, using the lower overdrive level can reduce the leakage current and thus the device current.

The BQ769142 device supports a system with FETs in a series or parallel configuration, where the parallel configuration includes a separate path for the charger connection versus the discharge (load) connection. The control logic for the device operates slightly differently in these two cases, which is set based on the configuration setting.

The FET drivers in the BQ769142 device can be controlled in several different manner, depending on customer requirements:

Fully autonomous
The BQ769142 device can detect protection faults and autonomously disable the FETs, monitor for a recovery condition, and autonomously reenable the FETs, without requiring any host processor involvement.
Partially autonomous
The BQ769142 device can detect protection faults and autonomously disable the FETs. When the host receives an interrupt and recognizes the fault, the host can send commands across the digital communications interface to keep the FETs off until the host decides to release them.
Alternatively, the host can assert the CFETOFF or DFETOFF pins to keep the FETs off. As long as these pins are asserted, the FETs are blocked from being reenabled. When these pins are deasserted, the BQ769142 will reenable the FETs if nothing is blocking them being reenabled (such as fault conditions still present, or the CFETOFF or DFETOFF pins are asserted).
Manual control
The BQ769142 device can detect protection faults and provide an interrupt to a host processor over the ALERT pin. The host processor can read the status information of the fault over the communication bus (if desired) and can quickly force the CHG or DSG FETs off by driving the CFETOFF or DFETOFF pins from the host processor, or commands over the digital communications interface.
When the host decides to allow the FETs to turn on again, it writes the appropriate command or deasserts the CFETOFF and DFETOFF pins, and the BQ769142 device will reenable the FETs if nothing is blocking them being reenabled.