SLUSE91B September   2020  – January 2022 BQ769142

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information BQ769142
    5. 7.5  Supply Current
    6. 7.6  Digital I/O
    7. 7.7  LD Pin
    8. 7.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 7.9  FUSE Pin Functionality
    10. 7.10 REG18 LDO
    11. 7.11 REG0 Pre-regulator
    12. 7.12 REG1 LDO
    13. 7.13 REG2 LDO
    14. 7.14 Voltage References
    15. 7.15 Coulomb Counter
    16. 7.16 Coulomb Counter Digital Filter (CC1)
    17. 7.17 Current Measurement Digital Filter (CC2)
    18. 7.18 Current Wake Detector
    19. 7.19 Analog-to-Digital Converter
    20. 7.20 Cell Balancing
    21. 7.21 Cell Open Wire Detector
    22. 7.22 Internal Temperature Sensor
    23. 7.23 Thermistor Measurement
    24. 7.24 Internal Oscillators
    25. 7.25 High-side NFET Drivers
    26. 7.26 Comparator-Based Protection Subsystem
    27. 7.27 Timing Requirements - I2C Interface, 100kHz Mode
    28. 7.28 Timing Requirements - I2C Interface, 400kHz Mode
    29. 7.29 Timing Requirements - HDQ Interface
    30. 7.30 Timing Requirements - SPI Interface
    31. 7.31 Interface Timing Diagrams
    32. 7.32 Typical Characteristics
  8. 8 Device Description
    1. 8.1 Overview
    2. 8.2 BQ769142 Device Versions
    3. 8.3 Functional Block Diagram
    4. 8.4 Diagnostics
  9. 9 Device Configuration
    1. 9.1 Commands and Subcommands
    2. 9.2 Configuration Using OTP or Registers
    3. 9.3 Device Security
    4. 9.4 Scratchpad Memory
  10. 10Measurement Subsystem
    1. 10.1  Voltage Measurement
      1. 10.1.1 Voltage Measurement Schedule
      2. 10.1.2 Using VC Pins for Cells Versus Interconnect
      3. 10.1.3 Cell 1 Voltage Validation During SLEEP Mode
    2. 10.2  General Purpose ADCIN Functionality
    3. 10.3  Coulomb Counter and Digital Filters
    4. 10.4  Synchronized Voltage and Current Measurement
    5. 10.5  Internal Temperature Measurement
    6. 10.6  Thermistor Temperature Measurement
    7. 10.7  Factory Trim of Voltage ADC
    8. 10.8  Voltage Calibration (ADC Measurements)
    9. 10.9  Voltage Calibration (COV and CUV Protections)
    10. 10.10 Current Calibration
    11. 10.11 Temperature Calibration
  11. 11Primary and Secondary Protection Subsystems
    1. 11.1 Protections Overview
    2. 11.2 Primary Protections
    3. 11.3 Secondary Protections
    4. 11.4 High-Side NFET Drivers
    5. 11.5 Protection FETs Configuration and Control
      1. 11.5.1 FET Configuration
      2. 11.5.2 PRECHARGE and PREDISCHARGE Modes
    6. 11.6 Load Detect Functionality
  12. 12Device Hardware Features
    1. 12.1  Voltage References
    2. 12.2  ADC Multiplexer
    3. 12.3  LDOs
      1. 12.3.1 Preregulator Control
      2. 12.3.2 REG1 and REG2 LDO Controls
    4. 12.4  Standalone Versus Host Interface
    5. 12.5  Multifunction Pin Controls
    6. 12.6  RST_SHUT Pin Operation
    7. 12.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
    8. 12.8  ALERT Pin Operation
    9. 12.9  DDSG and DCHG Pin Operation
    10. 12.10 Fuse Drive
    11. 12.11 Cell Open Wire
    12. 12.12 Low Frequency Oscillator
    13. 12.13 High Frequency Oscillator
  13. 13Device Functional Modes
    1. 13.1 Overview
    2. 13.2 NORMAL Mode
    3. 13.3 SLEEP Mode
    4. 13.4 DEEPSLEEP Mode
    5. 13.5 SHUTDOWN Mode
    6. 13.6 CONFIG_UPDATE Mode
  14. 14Serial Communications Interface
    1. 14.1 Serial Communications Overview
    2. 14.2 I2C Communications
    3. 14.3 SPI Communications
      1. 14.3.1 SPI Protocol
    4. 14.4 HDQ Communications
  15. 15Cell Balancing
    1. 15.1 Cell Balancing Overview
  16. 16Application and Implementation
    1. 16.1 Application Information
    2. 16.2 Typical Applications
      1. 16.2.1 Design Requirements (Example)
      2. 16.2.2 Detailed Design Procedure
      3. 16.2.3 Application Performance Plot
      4. 16.2.4 Calibration Process
    3. 16.3 Random Cell Connection Support
    4. 16.4 Startup Timing
    5. 16.5 FET Driver Turn-Off
    6. 16.6 Unused Pins
  17. 17Power Supply Requirements
  18. 18Layout
    1. 18.1 Layout Guidelines
    2. 18.2 Layout Example
  19. 19Device and Documentation Support
    1. 19.1 Third-Party Products Disclaimer
    2. 19.2 Documentation Support
    3. 19.3 Support Resources
    4. 19.4 Trademarks
    5. 19.5 Electrostatic Discharge Caution
    6. 19.6 Glossary
  20. 20Mechanical, Packaging, Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.8 Voltage Calibration (ADC Measurements)

The BQ769142 device includes an optional capability for the customer to calibrate each cell voltage gain and the gain for the stack voltage, the PACK pin voltage, and the LD pin voltage individually, and multifunction pin general ADC measurements. An offset calibration value Calibration:Vcell Offset:Vcell Offset is included for use with the cell voltage measurements, and Calibration:Vdiv Offset:Vdiv Offset is used with the TOS (stack), PACK, and LD voltage measurements. The cell voltage gains determined during calibration are written in Calibration:Voltage:Cell 1 Gain – Cell 14 Gain, where Cell 1 Gain is used for the measurement of VC1–VC0, Cell 2 Gain is used for the measurement of VC2–VC1, and so forth. Similarly, the calibration voltage gain for the TOS voltage should be written in Calibration:Voltage:TOS Gain, the PACK pin voltage gain in Calibration:Voltage:Pack Gain, the LD pin voltage gain in Calibration:Voltage:LD Gain, and multifunction pin general purpose ADCIN measurement gain in Calibration:Voltage:ADC Gain.

If values for the calibration gain configuration are not written, the BQ769142 device uses a factory trim or default values for the respective gain values. When a calibration gain configuration value is written, the device will use that in place of any factory trim or default gain. The raw ADC measurement data (in units of counts) is corrected by first subtracting a stored offset trim value, then the gain is applied, then the Calibration:Vcell Offset:Vcell Offset (for cell voltage measurements) or the Calibration:Vdiv Offset:Vdiv Offset (for TOS, PACK, or LD voltage measurements) is subtracted, before the final voltage value is reported.

The factory trim values for the Cell Gain parameters can be read from the Cell Gain data memory registers while in FULLACCESS mode but not in CONFIG_UPDATE mode, if the data memory values have not been overwritten. While in CONFIG_UPDATE mode, the Cell Gain values will read back either with all zeros, if they have not been overwritten, or whatever values have been written to these registers. Upon exiting CONFIG_UPDATE mode, readback of the Cell Gain parameters will provide the values presently used in operation.

Further details on calibration procedures can be found in the BQ769142 Technical Reference Manual.

The effective fullscale digital range of the cell measurement is 5 × VREF1, and the effective fullscale digital range of the ADCIN measurement is 1.667 × VREF1, although the voltages applied for these measurements should be limited based on the specifications in Section 7. Using a value for VREF1 of 1.212 V, the nominal gain for the cell measurements is 12120, while the nominal gain for the ADCIN measurements is 4040. The reported voltages are calculated as:

Cell # Voltage() = Calibration:Voltage:Cell # Gain × (16-bit ADC counts) / 65536 – Calibration:Vcell Offset:Vcell Offset
Stack Voltage() = Calibration:Voltage:TOS Gain × (16-bit ADC counts) / 65536 – Calibration:Vdiv Offset:Vdiv Offset
PACK Pin Voltage() = Calibration:Voltage:Pack Gain × (16-bit ADC counts) / 65536 – Calibration:Vdiv Offset:Vdiv Offset
LD Pin Voltage() = Calibration:Voltage:LD Gain × (16-bit ADC counts) / 65536 – Calibration:Vdiv Offset:Vdiv Offset
ADCIN Voltage = Calibration:Voltage:ADC Gain × (16-bit ADC counts) / 65536
Note: Cell # Voltage() and Calibration:Vcell Offset:Vcell Offset have units of mV. The divider voltages (Stack Voltage(), PACK Pin Voltage(), LD Pin Voltage()), and Calibration:Vdiv Offset:Vdiv Offset all have units of userV.