SLUSBK2I October   2013  – March 2022 BQ76920 , BQ76930 , BQ76940

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Versions
    2. 6.2 BQ76920 Pin Diagram
    3. 6.3 BQ76930 Pin Diagram
    4. 6.4 BQ76940 Pin Diagram
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Subsystems
        1. 8.3.1.1 Measurement Subsystem Overview
          1. 8.3.1.1.1 Data Transfer to the Host Controller
          2. 8.3.1.1.2 14-Bit ADC
            1. 8.3.1.1.2.1 Optional Real-Time Calibration Using the Host Microcontroller
          3. 8.3.1.1.3 16-Bit CC
          4. 8.3.1.1.4 External Thermistor
          5. 8.3.1.1.5 Die Temperature Monitor
          6. 8.3.1.1.6 16-Bit Pack Voltage
          7. 8.3.1.1.7 System Scheduler
        2. 8.3.1.2 Protection Subsystem
          1. 8.3.1.2.1 Integrated Hardware Protections
          2. 8.3.1.2.2 Reduced Test Time
        3. 8.3.1.3 Control Subsystem
          1. 8.3.1.3.1 FET Driving (CHG AND DSG)
            1. 8.3.1.3.1.1 High-Side FET Driving
          2. 8.3.1.3.2 Load Detection
          3. 8.3.1.3.3 Cell Balancing
          4. 8.3.1.3.4 Alert
          5. 8.3.1.3.5 Output LDO
        4. 8.3.1.4 Communications Subsystem
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 SHIP Mode
    5. 8.5 Register Maps
      1. 8.5.1 Register Details
      2. 8.5.2 Read-Only Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Timing
      2. 9.1.2 Random Cell Connection
      3. 9.1.3 Power Pin Diodes
      4. 9.1.4 Alert Pin
      5. 9.1.5 Sense Inputs
      6. 9.1.6 TSn Pins
      7. 9.1.7 Unused Pins
      8. 9.1.8 Configuring Alternative Cell Counts
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step-by-Step Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.3.1.3.3 Cell Balancing

Both internal and external passive cell balancing options are fully supported by the BQ76920, while external cell balancing is recommended for BQ76930 and BQ76940. It is left to the host controller to determine the exact balancing algorithm to be used in any given system. Each BQ769x0 device provides the cell voltages and balancing drivers to enable this. If using the internal cell balance drivers, up to 50 mA may be balanced per cell. If using external cell balancing, much higher balancing currents may be employed.

To activate a particular cell balancing channel, simply set the corresponding bit for that cell in the CELLBAL1, CELLBAL2, or CELLBAL3 register. For example, VC1–VC0 is enabled by setting [CB1], while VC12–VC11 is set through [CB12].

Multiple cells may be simultaneously balanced. It is left to the user’s discretion to determine the ideal number of cells to concurrently balance. Adjacent cells should not be balanced simultaneously. This may cause cell pins to exceed their absolute maximum conditions and is also not recommended for external balancing implementations. Additionally, if internal balancing is used, care should be taken to avoid exceeding package power dissipation ratings.

Note:

The host controller must ensure that no two adjacent cells are balanced simultaneously within each set of the following:

  • VC1–VC5
  • VC6–VC10
  • VC11–VC15

The total duty cycle devoted to balancing is approximately 70% per 250 ms. This is because a portion of the 250 ms is allotted for normal cell voltage measurements through the ADC.

If [ADC_EN] =1, OV and UV protections are not affected by cell balancing, since the cell balancing is temporarily suspended for a small slice of time every 250 ms during which the cell voltage readings are taken. This ensures that the OV and UV protections do not accidentally trigger, or miss an actual OV/UV condition on the cells while balancing is enabled.

Note:

All cell balancing control bits in CELLBAL1, CELLBAL2, and CELLBAL3 are automatically cleared under the following events, and must be explicitly rewritten by the host microcontroller following clearing of the event:

  • DEVICE_XREADY is set
  • Enters NORMAL mode from SHIP mode