SLUSBK2I October   2013  – March 2022 BQ76920 , BQ76930 , BQ76940

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Versions
    2. 6.2 BQ76920 Pin Diagram
    3. 6.3 BQ76930 Pin Diagram
    4. 6.4 BQ76940 Pin Diagram
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Subsystems
        1. 8.3.1.1 Measurement Subsystem Overview
          1. 8.3.1.1.1 Data Transfer to the Host Controller
          2. 8.3.1.1.2 14-Bit ADC
            1. 8.3.1.1.2.1 Optional Real-Time Calibration Using the Host Microcontroller
          3. 8.3.1.1.3 16-Bit CC
          4. 8.3.1.1.4 External Thermistor
          5. 8.3.1.1.5 Die Temperature Monitor
          6. 8.3.1.1.6 16-Bit Pack Voltage
          7. 8.3.1.1.7 System Scheduler
        2. 8.3.1.2 Protection Subsystem
          1. 8.3.1.2.1 Integrated Hardware Protections
          2. 8.3.1.2.2 Reduced Test Time
        3. 8.3.1.3 Control Subsystem
          1. 8.3.1.3.1 FET Driving (CHG AND DSG)
            1. 8.3.1.3.1.1 High-Side FET Driving
          2. 8.3.1.3.2 Load Detection
          3. 8.3.1.3.3 Cell Balancing
          4. 8.3.1.3.4 Alert
          5. 8.3.1.3.5 Output LDO
        4. 8.3.1.4 Communications Subsystem
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 SHIP Mode
    5. 8.5 Register Maps
      1. 8.5.1 Register Details
      2. 8.5.2 Read-Only Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Timing
      2. 9.1.2 Random Cell Connection
      3. 9.1.3 Power Pin Diodes
      4. 9.1.4 Alert Pin
      5. 9.1.5 Sense Inputs
      6. 9.1.6 TSn Pins
      7. 9.1.7 Unused Pins
      8. 9.1.8 Configuring Alternative Cell Counts
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step-by-Step Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Typical conditions are measured at 25°C with nominal BAT voltages of 18 V (BQ76920), 36 V (BQ76930), or 48 V (BQ76940) with VCELL = 4 V. Min and max values include full recommended operating condition temperature range from –40°C to +85°C. Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition sections.
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY CURRENTS
IDD NORMAL mode: ADC off, CC off Sum of ICC_BAT and ICC_REGSRC currents 40 60 µA
NORMAL mode: ADC on, CC off 60 90
NORMAL mode: ADC off, CC on 110 165
NORMAL mode: ADC on, CC on 130 195
ICC_BAT NORMAL mode: ADC off Into BAT pin 30 45
NORMAL mode: ADC on 50 75
ICC_REGSRC NORMAL mode: CC off Into REGSRC pin 10 15
NORMAL mode: CC on 80 120
ISHIP SHIP/SHUTDOWN mode Device in full shutdown, only VSTUP/BG and BOOT detector on 0.6 1.8
LEAKAGE AND OFFSET CURRENTS
dINOM NORMAL mode supply current offset Measured into VC5x (BQ76930, BQ76940) and VC10x (BQ76940) –5 ±2.5 5 µA
dISHIP SHIP mode supply current offset –1.0 ±0.1 1.0
dIALERT Supply current when ALERT active Measured into VC5x (BQ76930, BQ76940) or added to BAT (BQ76920) 15 25
dICELL Cell measurement input current Measured into VC0–VC15 except VC5, VC10, VC15 –0.3 ±0.1 0.3
Measured into VC5, VC10, VC15 0.5
ILKG Terminal input leakage 1
INTERNAL POWER CONTROL (STARTUP and SHUTDOWN)
VPORA Analog POR threshold VBAT rising. See (4). 4 5 V
VSHUT Shutdown voltage VBAT falling. See (4). 3.6 V
tI2CSTARTUP Time delay after boot signal on TS1 before I2C communications allowed Delay after boot sequence when I2C communication is allowed 1 ms
tBOOTREADY Device boot startup delay Delay after boot signal when device has completed full boot-up sequence 10 ms
TSHUTD Thermal shutdown voltage 100 150 °C
MEASUREMENT SCHEDULE
tVCELL Cell voltage measurement interval BQ76920, BQ76930, BQ76940 250 ms
tINDCELL Individual cell measurement time Per cell, balancing off 50
Per cell, balancing on 12.5
tCB_RELAX Cell balancing relaxation time before cell voltage measured 12.5
tTEMP_DEC Temperature measurement decimation time Measurement duration for temperature reading 12.5
tBAT Pack voltage calculation interval 250
tTEMP Temperature measurement interval Period of measurement of either TS1/TS2/TS3 or internal die temp 2 s
14-BIT ADC FOR CELL VOLTAGE AND TEMPERATURE MEASUREMENT
ADCRANGE ADC measurement recommend operation range VCELL measurements 2 5 V
TS/Temp measurements 0.3 3 V
ADCLSB ADC LSB value 382 µV
ADC ADC cell voltage accuracy at 25°C VCELL = 3.6 V – 4.3 V ±10 mV
VCELL = 3.2 V – 4.6 V ±15
VCELL = 2.0 V – 5.0 V ±25
ADC cell voltage accuracy 0°C to 60°C VCELL = 3.6 V – 4.3 V ±20
VCELL = 3.2 V – 4.6 V ±25
VCELL = 2.0 V – 5.0 V ±35
ADC cell voltage accuracy –40°C to 85°C VCELL = 3.6 V – 4.3 V –40 40
VCELL = 3.2 V – 4.6 V –40 40
VCELL = 2.0 V – 5.0 V –50 50
16-BIT CC FOR PACK CURRENT MEASUREMENT
CCRANGE CC input voltage range –200 200 mV
CCFSR CC full scale range –270 270 mV
CCLSB CC LSB value CC running constantly 8.44 µV
tCCREAD Conversion time Single conversion 250 ms
CCINL Integral nonlinearity 16-bit, best fit over input voltage range ± 200 mV ± 2 ± 40 LSB
CCOFFSET Offset error ± 1 ± 3 LSB
CCGAIN Gain error Over input voltage range ± 0.5% ± 1.5% FSR
CCGAINDRIFT Gain error drift Over input voltage range 150 PPM / °C
CCRIN Effective input resistance 2.5 MΩ
THERMISTOR BIAS
RTS Pull-up resistance TA = 25°C 9.85 10 10.15 kΩ
RTSDRIFT Pull-up resistance across temp TA = –40°C to 85°C 9.7 10.3 kΩ
DIETEMP
VDIETEMP25 Die temperature voltage TA = 25°C 1.20 V
VDIETEMPDRIFT Die temperature voltage drift –4.2 mV/°C
INTEGRATED HARDWARE PROTECTIONS
OVRANGE OV threshold range 0x2008 0x2FF8 ADC
UVRANGE UV threshold range 0x1000 0x1FF0 ADC
OVUVSTEP OV and UV threshold step size 16 LSB
UVMINQUAL UV minimum value to qualify Below UVMINQUAL, the cell is shorted (unused) 0x0518 ADC
OVDELAY OV delay timer options OV delay = 1 s 0.7 1 1.75 s
OV delay = 2 s 1.6 2 2.75
OV delay = 4 s 3.5 4 5
OV delay = 8 s 7 8 10
UVDELAY UV delay timer options UV delay = 1 s 0.7 1 1.75
UV delay = 4 s 3.5 4 5
UV delay = 8 s 7 8 10
UV delay = 16 s 14 16 20
OCDRANGE OCD threshold options Measured across (SRP–SRN)(2) 8 100 mV
OCDSTEP OCD threshold step size RSNS = 0 2.78 mV
RSNS = 1 5.56 mV
OCDDELAY OCD delay options See Note(3) 8 1280 ms
SCDRANGE SCD threshold options Measured across (SRP–SRN)(2) 22 200 mV
SCDSTEP SCD threshold step size RSNS = 0 11.1 mV
RSNS = 1 22.2 mV
SCDDELAY SCD delay options 35 70 105 µs
50 100 150 µs
140 200 260 µs
280 400 520 µs
tPROTACC Delay accuracy for OCD –20% 20%
OCOFFSET OCD and SCD voltage offset –2.5 2.5 mV
OCSCALEERR OCD and SCD scale accuracy –10% 10%
CHARGE AND DISCHARGE DRIVERS
VFETON CHG and DSG on REGSRC ≥ 12 V with load resistance of 10 MΩ 10 12 14 V
REGSRC < 12 V with load resistance of 10 MΩ REGSRC –2 REGSRC –1 REGSRC V
tFET_ON CHG and DSG ON rise time CHG/DSG driving an equivalent load capacitance of 10 nF, measured from 10% to 90% of VFETON 200 250 µs
tDSG_OFF DSG pull-down OFF fall time DSG driving an equivalent load capacitance of 10 nF, measured from 90% to 10% 60 90 µs
RCHG_OFF CHG pull-down OFF resistance to VSS When CHG disabled, CHG held at 12 V 750 1000 1250 kΩ
RDSG_OFF DSG pull-down OFF resistance to VSS When DSG disabled, DSG held at 12 V 1.75 2.50 4.25 kΩ
VLOAD_DETECT Load detection threshold 0.4 0.7 1.0 V
VCHG_CLAMP CHG clamp voltage If the CHG pin externally pulled high (through PACK–, if load applied), 500-µA max sink current into CHG pin. With CHG_ON bit cleared. 18 20 22 V
ALERT PIN
VALERT_OH ALERT output voltage high IOL = 1 mA REGOUT x 0.75 V
VALERT_OL ALERT output voltage low Unloaded REGOUT x 0.25 V
VALERT_IH ALERT input high ALERT externally forced high when internally driven low. See note (1). 1 1.5 V
RALERT_PD ALERT pin weak pulldown resistance when driven low Measured into ALERT pin with ALERT = REGOUT 0.8 2.5 8 MΩ
CELL BALANCING DRIVER
RDSFET Internal cell balancing driver resistance VCELL = 3.6 V 1 5 10 Ω
XBAL Cell balancing duty cycle when enabled Every 250 ms 70%
EXTERNAL REGULATOR
VEXTLDO External LDO voltage options Nominal values, TI factory programmed, unloaded, across temp 2.45 2.50 2.55 V
3.20 3.30 3.40 V
VEXTLDO_LN Line regulation REGSRC pin stepped from 6 to 25 V, with 10-mA load, in 100 µs 100 mV
VEXTLDO_LD Load regulation IREGOUT = 0 mA to 10 mA –4% 4%
VEXTLDO_DC External LDO minimum voltage under DC load REGOUT = 10-mA DC, 2.5-V version 2.4 V
REGOUT = 20-mA DC, 2.5-V version 2.3 V
REGOUT = 10-mA DC, 3.3-V version 3.15 V
REGOUT = 20-mA DC, 3.3-V version 3.05 V
IEXTLDO_LIMIT External LDO current limit REGOUT = 0 V 30 38 45 mA
BOOT DETECTOR
VBOOT Boot threshold voltage Measured at TS1 pin with device in SHIP mode. Below MIN, the device does not boot up. Above MAX, the device boots up. 300 1000 mV
tBOOT_max Boot threshold application time Measured at TS1 pin. Below MIN, the device does not boot up. Above MAX, the device boots up. 10 2000 µs
(1) MIN specifies the threshold below which the device will never register that an external alert has occurred. MAX specifies the minimum threshold above which the device will always register that an external alert has occurred.
(2) Values indicate nominal thresholds only. For min and max variation, apply OCOFFSET and OCSCALERR.
(3) Values indicate nominal thresholds only. For min and max variation, apply tPROTACC.
(4) Measured at each VBAT