SLUSBK2I October   2013  – March 2022 BQ76920 , BQ76930 , BQ76940

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Versions
    2. 6.2 BQ76920 Pin Diagram
    3. 6.3 BQ76930 Pin Diagram
    4. 6.4 BQ76940 Pin Diagram
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Subsystems
        1. 8.3.1.1 Measurement Subsystem Overview
          1. 8.3.1.1.1 Data Transfer to the Host Controller
          2. 8.3.1.1.2 14-Bit ADC
            1. 8.3.1.1.2.1 Optional Real-Time Calibration Using the Host Microcontroller
          3. 8.3.1.1.3 16-Bit CC
          4. 8.3.1.1.4 External Thermistor
          5. 8.3.1.1.5 Die Temperature Monitor
          6. 8.3.1.1.6 16-Bit Pack Voltage
          7. 8.3.1.1.7 System Scheduler
        2. 8.3.1.2 Protection Subsystem
          1. 8.3.1.2.1 Integrated Hardware Protections
          2. 8.3.1.2.2 Reduced Test Time
        3. 8.3.1.3 Control Subsystem
          1. 8.3.1.3.1 FET Driving (CHG AND DSG)
            1. 8.3.1.3.1.1 High-Side FET Driving
          2. 8.3.1.3.2 Load Detection
          3. 8.3.1.3.3 Cell Balancing
          4. 8.3.1.3.4 Alert
          5. 8.3.1.3.5 Output LDO
        4. 8.3.1.4 Communications Subsystem
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 SHIP Mode
    5. 8.5 Register Maps
      1. 8.5.1 Register Details
      2. 8.5.2 Read-Only Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Timing
      2. 9.1.2 Random Cell Connection
      3. 9.1.3 Power Pin Diodes
      4. 9.1.4 Alert Pin
      5. 9.1.5 Sense Inputs
      6. 9.1.6 TSn Pins
      7. 9.1.7 Unused Pins
      8. 9.1.8 Configuring Alternative Cell Counts
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step-by-Step Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.1 Step-by-Step Design Procedure

  • Determine the number of series cells.
    • This value depends on the cell chemistry and the load requirements of the system. For example, to support a minimum battery voltage of 24 V using Li-CO2 type cells with a cell minimum voltage of 3.0 V, there needs to be at least 8-series cells.
  • Select the correct BQ769x0 device.
    • For 8-series cells, the BQ76930 is needed.
    • For the correct cell connections, see Table 9-3.
  • Select the correct protection FETs.
    • The BQ76930 uses a low-side drive suitable for N-CH FETs.
    • These FETs should be rated for the maximum:
      • Voltage, which should be approximately 5 V (DC) 10 V (peak) per series cell: for example, 40 V.
      • Current, which should be calculated based on both the maximum DC current and the maximum transient current with some margin: for example, 30 A.
      • Power Dissipation, which can be a factor of the RDS(ON) rating of the FET, the FET package, and the PCB design: for example, 5 W, assuming 5 mΩ RDS(ON).
  • Select the correct sense resistor.
    • The resistance value should be selected to maximize the input bandwidth use of the coulomb counter range, CCRANGE, as well as keeping the SCD and OCD thresholds in the available selections, and not exceed the absolute maximum ratings. The sense resistance RSNS is the threshold or input voltage divided by the current.
      • Using the normal max discharge current, RSNS = 200 mV / 10.0 A = 20 mΩ maximum.
      • However, considering the maximum SCD threshold of 200 mV and ISCD of 25 A , RSNS = 200 mV / 25 A = 8 mΩ maximum.
      • The maximum OCD threshold available is 100 mV, with the maximum current of 15 A, RSNS = 100 mV / 15.0 A = 6.7 mΩ maximum.
    • Further tolerance analysis (value tolerance, temperature variation, and so on) and PCB design margin should also be considered, so RSNS of 5 mΩ would be suitable with a 75-ppm temperature coefficient and power rating of 5 W.
    • With VSS referenced at the SRP terminal charge current creates a negative voltage on SRN. The 5 mΩ with 3 A charge current is within the absolute maximum range.
  • The BQ76930 is chosen, and so the REGSRC pin needs to be powered through a source follower circuit where the FET is used to provide current for REGSRC from the battery positive terminal while reducing the voltage to a suitable value for the IC.
    • The FET also dissipates the power resulting from the load current and dropped voltage external to the IC and care should be taken to ensure the correct dissipation ratings are specified by the chosen FET.
  • Configure the Current-based protection settings through PROTECT1 and PROTECT2:
    • Ideal SCD Threshold = 25 A × 5 mΩ = 125 mV.
      • However, the closest options are 111 mV (0x03) and 133 mV (0x04) providing 22.2 A and 26.6 A, respectively. Both options have the RSNS bit = 1.
      • 0x03 (22.2 A) will be used in this example.
    • The SCD delay threshold setting for a 100 µs delay is 0x01.
    • Therefore, PROTECT1 should be programmed with 0x8B.
    • Ideal OCD Threshold = 15 A × 5 mΩ = 75 mV.
      • However, the closest options are 72 mV (0x0A) and 78 mV (0x0B), providing 14.4 A and 15.6 A, respectively. Both options have the RSNS bit = 1.
      • 0x0A (14.4A) will be used in this example.
    • The OCD delay threshold setting for a 320-ms delay is 0x05.
    • Therefore, PROTECT2 should be programmed with 0x5B.
    Note:

    Care should be taken when determining the setting of OV_TRIP and UV_TRIP as these are ADC value outputs and correlation to cell voltage also requires consideration of the ADC GAIN and ADC OFFSET registers. More specific details can be found in Section 8.3.1.2.

  • Configure the Voltage-based protection settings through OV_TRIP, UV_TRIP and PROTECT3:
    • The selected OV Threshold is 4.30 V. If ADCOFFSET is 0 and GAIN is 382, the desired threshold is 11257 or 0x2BF9.
      • Therefore, OV_TRIP should be programmed with 0xBF.
    • The selected UV Threshold is 2.5 V. If ADCOFFSET is 0 and GAIN is 382, the desired threshold is 6545 or 0x1991.
      • Therefore, UV_TRIP should be programmed with 0x99.
    • The selected OV Delay is 2 s and the selected UV Delay is 4 s.
      • Therefore, PROTECT3 should be programmed with 0x50.