SLUSBK2I October   2013  – March 2022 BQ76920 , BQ76930 , BQ76940

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Versions
    2. 6.2 BQ76920 Pin Diagram
    3. 6.3 BQ76930 Pin Diagram
    4. 6.4 BQ76940 Pin Diagram
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Subsystems
        1. 8.3.1.1 Measurement Subsystem Overview
          1. 8.3.1.1.1 Data Transfer to the Host Controller
          2. 8.3.1.1.2 14-Bit ADC
            1. 8.3.1.1.2.1 Optional Real-Time Calibration Using the Host Microcontroller
          3. 8.3.1.1.3 16-Bit CC
          4. 8.3.1.1.4 External Thermistor
          5. 8.3.1.1.5 Die Temperature Monitor
          6. 8.3.1.1.6 16-Bit Pack Voltage
          7. 8.3.1.1.7 System Scheduler
        2. 8.3.1.2 Protection Subsystem
          1. 8.3.1.2.1 Integrated Hardware Protections
          2. 8.3.1.2.2 Reduced Test Time
        3. 8.3.1.3 Control Subsystem
          1. 8.3.1.3.1 FET Driving (CHG AND DSG)
            1. 8.3.1.3.1.1 High-Side FET Driving
          2. 8.3.1.3.2 Load Detection
          3. 8.3.1.3.3 Cell Balancing
          4. 8.3.1.3.4 Alert
          5. 8.3.1.3.5 Output LDO
        4. 8.3.1.4 Communications Subsystem
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 SHIP Mode
    5. 8.5 Register Maps
      1. 8.5.1 Register Details
      2. 8.5.2 Read-Only Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Timing
      2. 9.1.2 Random Cell Connection
      3. 9.1.3 Power Pin Diodes
      4. 9.1.4 Alert Pin
      5. 9.1.5 Sense Inputs
      6. 9.1.6 TSn Pins
      7. 9.1.7 Unused Pins
      8. 9.1.8 Configuring Alternative Cell Counts
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step-by-Step Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Register Maps

NameAddrD7D6D5D4D3D2D1D0
SYS_STAT0x00CC_READYRSVDDEVICE_
XREADY		OVRD_
ALERT		UVOVSCDOCD
CELLBAL10x01RSVDRSVDRSVDCB<5:1>
CELLBAL2(1)0x02RSVDRSVDRSVDCB<10:6>
CELLBAL3(2)0x03RSVDRSVDRSVDCB<15:11>
SYS_CTRL10x04LOAD_
PRESENT		RSVDRSVDADC_ENTEMP_SELRSVDSHUT_ASHUT_B
SYS_CTRL20x05DELAY_DISCC_ENCC_
ONESHOT		RSVDDSG_ONCHG_ON
PROTECT10x06RSNSRSVDRSVDSCD_DELAYSCD_THRESH
PROTECT20x07RSVDOCD_DELAYOCD_THRESH
PROTECT30x08UV_DELAYOV_DELAYRSVD
OV_TRIP0x09OV_THRESH
UV_TRIP0x0AUV_THRESH
CC_CFG0x0BRSVDRSVDMust be programmed to 0x19
VC1_HI0x0CRSVDRSVD<13:8>
VC1_LO0x0D<7:0>
VC2_HI0x0ERSVDRSVD<13:8>
VC2_LO0x0F<7:0>
VC3_HI0x10RSVDRSVD<13:8>
VC3_LO0x11<7:0>
VC4_HI0x12RSVDRSVD<13:8>
VC4_LO0x13<7:0>
VC5_HI0x14RSVDRSVD<13:8>
VC5_LO0x15<7:0>
VC6_HI(1)0x16RSVDRSVD<13:8>
VC6_LO(1)0x17<7:0>
VC7_HI(1)0x18RSVDRSVD<13:8>
VC7_LO(1)0x19<7:0>
VC8_HI(1)0x1ARSVDRSVD<13:8>
VC8_LO(1)0x1B<7:0>
VC9_HI(1)0x1CRSVDRSVD<13:8>
VC9_LO(1)0x1D<7:0>
VC10_HI(1)0x1ERSVDRSVD<13:8>
VC10_LO(1)0x1F<7:0>
VC11_HI(2)0x20RSVDRSVD<13:8>
VC11_LO(2)0x21<7:0>
VC12_HI(2)0x22RSVDRSVD<13:8>
VC12_LO(2)0x23<7:0>
VC13_HI(2)0x24RSVDRSVD<13:8>
VC13_LO(2)0x25<7:0>
VC14_HI(2)0x26RSVDRSVD<13:8>
VC14_LO(2)0x27<7:0>
VC15_HI(2)0x28RSVDRSVD<13:8>
VC15_LO(2)0x29<7:0>
BAT_HI0x2A<15:8>
BAT_LO0x2B<7:0>
TS1_HI0x2CRSVDRSVD<13:8>
TS1_LO0x2D<7:0>
TS2_HI(1)0x2ERSVDRSVD<13:8>
TS2_LO(1)0x2F<7:0>
TS3_HI(2)0x30RSVDRSVD<13:8>
TS3_LO(2)0x31<7:0>
CC_HI0x32<15:8>
CC_LO0x33<7:0>
ADCGAIN10x50RSVDADCGAIN<4:3>RSVD
ADCOFFSET0x51ADCOFFSET<7:0>
ADCGAIN20x59ADCGAIN<2:0>RSVD
(1) These registers are only valid for BQ76930 and BQ76940.
(2) These registers are only valid for BQ76940.