SLUSE14B December   2020  – December 2021 BQ76942

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information BQ76942
    5. 7.5  Supply Current
    6. 7.6  Digital I/O
    7. 7.7  LD Pin
    8. 7.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 7.9  FUSE Pin Functionality
    10. 7.10 REG18 LDO
    11. 7.11 REG0 Pre-regulator
    12. 7.12 REG1 LDO
    13. 7.13 REG2 LDO
    14. 7.14 Voltage References
    15. 7.15 Coulomb Counter
    16. 7.16 Coulomb Counter Digital Filter (CC1)
    17. 7.17 Current Measurement Digital Filter (CC2)
    18. 7.18 Current Wake Detector
    19. 7.19 Analog-to-Digital Converter
    20. 7.20 Cell Balancing
    21. 7.21 Cell Open Wire Detector
    22. 7.22 Internal Temperature Sensor
    23. 7.23 Thermistor Measurement
    24. 7.24 Internal Oscillators
    25. 7.25 High-Side NFET Drivers
    26. 7.26 Comparator-Based Protection Subsystem
    27. 7.27 Timing Requirements – I2C Interface, 100kHz Mode
    28. 7.28 Timing Requirements – I2C Interface, 400kHz Mode
    29. 7.29 Timing Requirements – HDQ Interface
    30. 7.30 Timing Requirements – SPI Interface
    31. 7.31 Interface Timing Diagrams
    32. 7.32 Typical Characteristics
  8. 8 Device Description
    1. 8.1 Overview
    2. 8.2 BQ76942 Device Versions
    3. 8.3 Functional Block Diagram
    4. 8.4 Diagnostics
  9. 9 Device Configuration
    1. 9.1 Commands and Subcommands
    2. 9.2 Configuration Using OTP or Registers
    3. 9.3 Device Security
    4. 9.4 Scratchpad Memory
  10. 10Measurement Subsystem
    1. 10.1  Voltage Measurement
      1. 10.1.1 Voltage Measurement Schedule
      2. 10.1.2 Usage of VC Pins for Cells Versus Interconnect
      3. 10.1.3 Cell 1 Voltage Validation During SLEEP Mode
    2. 10.2  General Purpose ADCIN Functionality
    3. 10.3  Coulomb Counter and Digital Filters
    4. 10.4  Synchronized Voltage and Current Measurement
    5. 10.5  Internal Temperature Measurement
    6. 10.6  Thermistor Temperature Measurement
    7. 10.7  Factory Trim of Voltage ADC
    8. 10.8  Voltage Calibration (ADC Measurements)
    9. 10.9  Voltage Calibration (COV and CUV Protections)
    10. 10.10 Current Calibration
    11. 10.11 Temperature Calibration
  11. 11Primary and Secondary Protection Subsystems
    1. 11.1 Protections Overview
    2. 11.2 Primary Protections
    3. 11.3 Secondary Protections
    4. 11.4 High-Side NFET Drivers
    5. 11.5 Protection FETs Configuration and Control
      1. 11.5.1 FET Configuration
      2. 11.5.2 PRECHARGE and PREDISCHARGE Modes
    6. 11.6 Load Detect Functionality
  12. 12Device Hardware Features
    1. 12.1  Voltage References
    2. 12.2  ADC Multiplexer
    3. 12.3  LDOs
      1. 12.3.1 Preregulator Control
      2. 12.3.2 REG1 and REG2 LDO Controls
    4. 12.4  Standalone Versus Host Interface
    5. 12.5  Multifunction Pin Controls
    6. 12.6  RST_SHUT Pin Operation
    7. 12.7  CFETOFF, DFETOFF, BOTHOFF Pin Functionality
    8. 12.8  ALERT Pin Operation
    9. 12.9  DDSG and DCHG Pin Operation
    10. 12.10 Fuse Drive
    11. 12.11 Cell Open Wire
    12. 12.12 Low Frequency Oscillator
    13. 12.13 High Frequency Oscillator
  13. 13Device Functional Modes
    1. 13.1 Overview
    2. 13.2 NORMAL Mode
    3. 13.3 SLEEP Mode
    4. 13.4 DEEPSLEEP Mode
    5. 13.5 SHUTDOWN Mode
    6. 13.6 CONFIG_UPDATE Mode
  14. 14Serial Communications Interface
    1. 14.1 Serial Communications Overview
    2. 14.2 I2C Communications Subsystem
    3. 14.3 SPI Communications Interface
      1. 14.3.1 SPI Protocol
    4. 14.4 HDQ Communications Interface
  15. 15Cell Balancing
    1. 15.1 Cell Balancing Overview
  16. 16Application and Implementation
    1. 16.1 Application Information
    2. 16.2 Typical Applications
      1. 16.2.1 Design Requirements (Example)
      2. 16.2.2 Detailed Design Procedure
      3. 16.2.3 Application Performance Plot
      4. 16.2.4 Calibration Process
      5. 16.2.5 Design Example
    3. 16.3 Random Cell Connection Support
    4. 16.4 Startup Timing
    5. 16.5 FET Driver Turn-Off
    6. 16.6 Unused Pins
  17. 17Power Supply Requirements
  18. 18Layout
    1. 18.1 Layout Guidelines
    2. 18.2 Layout Example
  19. 19Device and Documentation Support
    1. 19.1 Third-Party Products Disclaimer
    2. 19.2 Documentation Support
      1. 19.2.1 Receiving Notification of Documentation Updates
    3. 19.3 Support Resources
    4. 19.4 Trademarks
    5. 19.5 Electrostatic Discharge Caution
    6. 19.6 Glossary
  20. 20Mechanical, Packaging, Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13.3 SLEEP Mode

SLEEP mode is a reduced functionality state that can be optionally used to reduce power dissipation when there is little or no system load current or charging in progress, but still provides voltage at the battery pack terminals to keep the system active. At initial powerup, a configuration bit determines whether the device can enter SLEEP mode. After initialization, SLEEP mode can be allowed or disallowed using subcommands. Status bits are provided to indicate whether the device is presently allowed to enter SLEEP mode or not, and whether it is presently in SLEEP mode or not.

When the magnitude of the CC1 Current measurement falls below a programmable current threshold, the system is considered in relax mode, and the BQ76942 device autonomously transitions into SLEEP mode, if settings permit. During SLEEP mode, comparator-based protections operate the same as during NORMAL mode. ADC-based current, voltage, and temperature measurements are taken at programmable intervals. All temperature protections use the ADC measurements taken at these intervals, so they will update at a reduced rate during SLEEP mode.

The BQ76942 device exits SLEEP mode if a protection fault occurs, current begins flowing, a charger is attached, if forced by a subcommand, or if the RST_SHUT pin is asserted for < 1 s. When exiting based on current flow, the device quickly enables the FETs (if the CHG FET was off or the DSG FET was in source-follower mode), but the standard measurement loop does not restart until the next 1-s boundary occurs within the device timing. Therefore, new data may not be available for up to ≈1 s after the device exits SLEEP mode.

The coulomb counter ADC operates in a reduced power and speed mode to monitor current during SLEEP mode. The current is measured every 12 ms and, if it exceeds a programmable threshold in magnitude, the device quickly transitions back to NORMAL mode. In addition to this check, if CC1 Current measurement taken at each programmed interval exceeds this threshold, the device exits SLEEP mode.

The device monitors the PACK pin voltage and the top-of-stack voltage at each programmed measurement interval. If the PACK pin voltage is higher than the top-of-stack voltage by more than a programmable delta and the top-of-stack voltage is less than a programmed threshold, the device exits SLEEP mode. The BQ76942 device also includes a hysteresis on the SLEEP mode entrance to avoid the device quickly entering and exiting SLEEP mode based on a dynamic load. After transitioning to NORMAL mode, the device will not enter SLEEP mode again for a number of seconds given by the hysteresis setting.

During SLEEP mode, the DSG FET can be driven either using the charge pump or in source-follower mode (as described in High-side NFET Drivers). The CHG FET can be disabled or driven using the charge pump, based on the configuration setting.