SLUSE14B December   2020  – December 2021 BQ76942

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information BQ76942
    5. 7.5  Supply Current
    6. 7.6  Digital I/O
    7. 7.7  LD Pin
    8. 7.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 7.9  FUSE Pin Functionality
    10. 7.10 REG18 LDO
    11. 7.11 REG0 Pre-regulator
    12. 7.12 REG1 LDO
    13. 7.13 REG2 LDO
    14. 7.14 Voltage References
    15. 7.15 Coulomb Counter
    16. 7.16 Coulomb Counter Digital Filter (CC1)
    17. 7.17 Current Measurement Digital Filter (CC2)
    18. 7.18 Current Wake Detector
    19. 7.19 Analog-to-Digital Converter
    20. 7.20 Cell Balancing
    21. 7.21 Cell Open Wire Detector
    22. 7.22 Internal Temperature Sensor
    23. 7.23 Thermistor Measurement
    24. 7.24 Internal Oscillators
    25. 7.25 High-Side NFET Drivers
    26. 7.26 Comparator-Based Protection Subsystem
    27. 7.27 Timing Requirements – I2C Interface, 100kHz Mode
    28. 7.28 Timing Requirements – I2C Interface, 400kHz Mode
    29. 7.29 Timing Requirements – HDQ Interface
    30. 7.30 Timing Requirements – SPI Interface
    31. 7.31 Interface Timing Diagrams
    32. 7.32 Typical Characteristics
  8. 8 Device Description
    1. 8.1 Overview
    2. 8.2 BQ76942 Device Versions
    3. 8.3 Functional Block Diagram
    4. 8.4 Diagnostics
  9. 9 Device Configuration
    1. 9.1 Commands and Subcommands
    2. 9.2 Configuration Using OTP or Registers
    3. 9.3 Device Security
    4. 9.4 Scratchpad Memory
  10. 10Measurement Subsystem
    1. 10.1  Voltage Measurement
      1. 10.1.1 Voltage Measurement Schedule
      2. 10.1.2 Usage of VC Pins for Cells Versus Interconnect
      3. 10.1.3 Cell 1 Voltage Validation During SLEEP Mode
    2. 10.2  General Purpose ADCIN Functionality
    3. 10.3  Coulomb Counter and Digital Filters
    4. 10.4  Synchronized Voltage and Current Measurement
    5. 10.5  Internal Temperature Measurement
    6. 10.6  Thermistor Temperature Measurement
    7. 10.7  Factory Trim of Voltage ADC
    8. 10.8  Voltage Calibration (ADC Measurements)
    9. 10.9  Voltage Calibration (COV and CUV Protections)
    10. 10.10 Current Calibration
    11. 10.11 Temperature Calibration
  11. 11Primary and Secondary Protection Subsystems
    1. 11.1 Protections Overview
    2. 11.2 Primary Protections
    3. 11.3 Secondary Protections
    4. 11.4 High-Side NFET Drivers
    5. 11.5 Protection FETs Configuration and Control
      1. 11.5.1 FET Configuration
      2. 11.5.2 PRECHARGE and PREDISCHARGE Modes
    6. 11.6 Load Detect Functionality
  12. 12Device Hardware Features
    1. 12.1  Voltage References
    2. 12.2  ADC Multiplexer
    3. 12.3  LDOs
      1. 12.3.1 Preregulator Control
      2. 12.3.2 REG1 and REG2 LDO Controls
    4. 12.4  Standalone Versus Host Interface
    5. 12.5  Multifunction Pin Controls
    6. 12.6  RST_SHUT Pin Operation
    7. 12.7  CFETOFF, DFETOFF, BOTHOFF Pin Functionality
    8. 12.8  ALERT Pin Operation
    9. 12.9  DDSG and DCHG Pin Operation
    10. 12.10 Fuse Drive
    11. 12.11 Cell Open Wire
    12. 12.12 Low Frequency Oscillator
    13. 12.13 High Frequency Oscillator
  13. 13Device Functional Modes
    1. 13.1 Overview
    2. 13.2 NORMAL Mode
    3. 13.3 SLEEP Mode
    4. 13.4 DEEPSLEEP Mode
    5. 13.5 SHUTDOWN Mode
    6. 13.6 CONFIG_UPDATE Mode
  14. 14Serial Communications Interface
    1. 14.1 Serial Communications Overview
    2. 14.2 I2C Communications Subsystem
    3. 14.3 SPI Communications Interface
      1. 14.3.1 SPI Protocol
    4. 14.4 HDQ Communications Interface
  15. 15Cell Balancing
    1. 15.1 Cell Balancing Overview
  16. 16Application and Implementation
    1. 16.1 Application Information
    2. 16.2 Typical Applications
      1. 16.2.1 Design Requirements (Example)
      2. 16.2.2 Detailed Design Procedure
      3. 16.2.3 Application Performance Plot
      4. 16.2.4 Calibration Process
      5. 16.2.5 Design Example
    3. 16.3 Random Cell Connection Support
    4. 16.4 Startup Timing
    5. 16.5 FET Driver Turn-Off
    6. 16.6 Unused Pins
  17. 17Power Supply Requirements
  18. 18Layout
    1. 18.1 Layout Guidelines
    2. 18.2 Layout Example
  19. 19Device and Documentation Support
    1. 19.1 Third-Party Products Disclaimer
    2. 19.2 Documentation Support
      1. 19.2.1 Receiving Notification of Documentation Updates
    3. 19.3 Support Resources
    4. 19.4 Trademarks
    5. 19.5 Electrostatic Discharge Caution
    6. 19.6 Glossary
  20. 20Mechanical, Packaging, Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.25 High-Side NFET Drivers

Typical values stated where TA = 25°C and VBAT = 55.0 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 55 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(FETON_HI) CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 8 V ≤ VBAT ≤ 55 V, VLD ≤ VDSG (1) CHG/DSG CL = 20 nF, charge pump high overdrive setting 10 11 13 V
V(FETON_HI_LOBAT) CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 4.7 V ≤ VBAT < 8 V, VLD ≤ VDSG (1) CHG/DSG CL = 20 nF, charge pump high overdrive setting 8 11 13 V
V(FETON_LO) CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 8 V ≤ VBAT ≤ 55 V, VLD ≤ VDSG (1) CHG/DSG CL = 20 nF, charge pump low overdrive setting 4.5 5.7 7 V
V(FETON_LO_LOBAT) CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 4.7 V ≤ VBAT < 8 V, VLD ≤ VDSG (1) CHG/DSG CL = 20 nF, charge pump low overdrive setting 3.5 5 7 V
V(SRCFOL_FETON) DSG on voltage with respect to BAT CHG/DSG CL = 20 nF, source follower mode 0 V
V(CHGFETOFF) CHG off voltage with respect to BAT CHG/DSG CL = 20 nF, steady state value 0.4 V
V(DSGFETOFF) DSG off voltage with respect to LD CHG/DSG CL = 20 nF, steady state value 0.7 V
t(FET_ON) CHG and DSG rise time CHG/DSG CL = 20 nF, RGATE = 100 Ω, 0.5 V to 4 V gate-source overdrive, charge pump mode(3) (4) 21 40 µs
t(CHGFETOFF) CHG fall time to BAT CHG CL = 20 nF, RGATE = 100 Ω, 90% to 10% of V(FETON) (4) 46 65 µs
t(DSGFETOFF) DSG fall time to LD DSG CL = 20 nF, RGATE = 100 Ω, 90% to 10% of V(FETON) (4) 2 20 µs
t(CP_START) Charge pump start up time CL = 20 nF, C(CP1) = 470 nF, 10% to 90% of V(FETON) 100 ms
C(CP1) Charge pump capacitor(2) 100 470 2200 nF
(1) When the DSG driver is enabled, the CHG driver is disabled, and a voltage is applied at the LD pin such that VLD > VDSG, the voltage at DSG will rise to ≈ VLD - 0.7 V
(2) Specified by design
(3) Specified by characterization
(4) RGATE can be optimized during design and system evaluation for best performance.  A larger value may be desired to avoid an overly fast FET turn off, which can result in a large voltage transient due to cell and harness inductance.