SLUSE14B December   2020  – December 2021 BQ76942

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information BQ76942
    5. 7.5  Supply Current
    6. 7.6  Digital I/O
    7. 7.7  LD Pin
    8. 7.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 7.9  FUSE Pin Functionality
    10. 7.10 REG18 LDO
    11. 7.11 REG0 Pre-regulator
    12. 7.12 REG1 LDO
    13. 7.13 REG2 LDO
    14. 7.14 Voltage References
    15. 7.15 Coulomb Counter
    16. 7.16 Coulomb Counter Digital Filter (CC1)
    17. 7.17 Current Measurement Digital Filter (CC2)
    18. 7.18 Current Wake Detector
    19. 7.19 Analog-to-Digital Converter
    20. 7.20 Cell Balancing
    21. 7.21 Cell Open Wire Detector
    22. 7.22 Internal Temperature Sensor
    23. 7.23 Thermistor Measurement
    24. 7.24 Internal Oscillators
    25. 7.25 High-Side NFET Drivers
    26. 7.26 Comparator-Based Protection Subsystem
    27. 7.27 Timing Requirements – I2C Interface, 100kHz Mode
    28. 7.28 Timing Requirements – I2C Interface, 400kHz Mode
    29. 7.29 Timing Requirements – HDQ Interface
    30. 7.30 Timing Requirements – SPI Interface
    31. 7.31 Interface Timing Diagrams
    32. 7.32 Typical Characteristics
  8. 8 Device Description
    1. 8.1 Overview
    2. 8.2 BQ76942 Device Versions
    3. 8.3 Functional Block Diagram
    4. 8.4 Diagnostics
  9. 9 Device Configuration
    1. 9.1 Commands and Subcommands
    2. 9.2 Configuration Using OTP or Registers
    3. 9.3 Device Security
    4. 9.4 Scratchpad Memory
  10. 10Measurement Subsystem
    1. 10.1  Voltage Measurement
      1. 10.1.1 Voltage Measurement Schedule
      2. 10.1.2 Usage of VC Pins for Cells Versus Interconnect
      3. 10.1.3 Cell 1 Voltage Validation During SLEEP Mode
    2. 10.2  General Purpose ADCIN Functionality
    3. 10.3  Coulomb Counter and Digital Filters
    4. 10.4  Synchronized Voltage and Current Measurement
    5. 10.5  Internal Temperature Measurement
    6. 10.6  Thermistor Temperature Measurement
    7. 10.7  Factory Trim of Voltage ADC
    8. 10.8  Voltage Calibration (ADC Measurements)
    9. 10.9  Voltage Calibration (COV and CUV Protections)
    10. 10.10 Current Calibration
    11. 10.11 Temperature Calibration
  11. 11Primary and Secondary Protection Subsystems
    1. 11.1 Protections Overview
    2. 11.2 Primary Protections
    3. 11.3 Secondary Protections
    4. 11.4 High-Side NFET Drivers
    5. 11.5 Protection FETs Configuration and Control
      1. 11.5.1 FET Configuration
      2. 11.5.2 PRECHARGE and PREDISCHARGE Modes
    6. 11.6 Load Detect Functionality
  12. 12Device Hardware Features
    1. 12.1  Voltage References
    2. 12.2  ADC Multiplexer
    3. 12.3  LDOs
      1. 12.3.1 Preregulator Control
      2. 12.3.2 REG1 and REG2 LDO Controls
    4. 12.4  Standalone Versus Host Interface
    5. 12.5  Multifunction Pin Controls
    6. 12.6  RST_SHUT Pin Operation
    7. 12.7  CFETOFF, DFETOFF, BOTHOFF Pin Functionality
    8. 12.8  ALERT Pin Operation
    9. 12.9  DDSG and DCHG Pin Operation
    10. 12.10 Fuse Drive
    11. 12.11 Cell Open Wire
    12. 12.12 Low Frequency Oscillator
    13. 12.13 High Frequency Oscillator
  13. 13Device Functional Modes
    1. 13.1 Overview
    2. 13.2 NORMAL Mode
    3. 13.3 SLEEP Mode
    4. 13.4 DEEPSLEEP Mode
    5. 13.5 SHUTDOWN Mode
    6. 13.6 CONFIG_UPDATE Mode
  14. 14Serial Communications Interface
    1. 14.1 Serial Communications Overview
    2. 14.2 I2C Communications Subsystem
    3. 14.3 SPI Communications Interface
      1. 14.3.1 SPI Protocol
    4. 14.4 HDQ Communications Interface
  15. 15Cell Balancing
    1. 15.1 Cell Balancing Overview
  16. 16Application and Implementation
    1. 16.1 Application Information
    2. 16.2 Typical Applications
      1. 16.2.1 Design Requirements (Example)
      2. 16.2.2 Detailed Design Procedure
      3. 16.2.3 Application Performance Plot
      4. 16.2.4 Calibration Process
      5. 16.2.5 Design Example
    3. 16.3 Random Cell Connection Support
    4. 16.4 Startup Timing
    5. 16.5 FET Driver Turn-Off
    6. 16.6 Unused Pins
  17. 17Power Supply Requirements
  18. 18Layout
    1. 18.1 Layout Guidelines
    2. 18.2 Layout Example
  19. 19Device and Documentation Support
    1. 19.1 Third-Party Products Disclaimer
    2. 19.2 Documentation Support
      1. 19.2.1 Receiving Notification of Documentation Updates
    3. 19.3 Support Resources
    4. 19.4 Trademarks
    5. 19.5 Electrostatic Discharge Caution
    6. 19.6 Glossary
  20. 20Mechanical, Packaging, Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.26 Comparator-Based Protection Subsystem

Typical values stated where TA = 25°C and VBAT = 55.0 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 55 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(OVP) Overvoltage detection range Nominal setting (50.6 mV steps) 1.012 V to 5.566 V in 50.6 mV steps V
V(OVP_ACC) Overvoltage detection voltage threshold accuracy(3) TA = +25°C, nominal setting between 1.012 V and 5.566 V(1) ±2 mV
TA = +25°C, nominal setting between 3.036 V and 5.06 V(1) –10 10 mV
TA = –10°C to +60°C, nominal setting between 1.012 V and 5.566 V(1) ±3 mV
TA = –10°C to +60°C, nominal setting between 3.036 V and 5.06 V(1) –15 15 mV
TA = –40°C to +85°C, nominal setting between 1.012 V and 5.566 V(1) ±5 mV
TA = –40°C to +85°C, nominal setting between 3.036 V and 5.06 V(1) –25 25 mV
V(OVP_DLY) Overvoltage detection delay(2) Nominal setting (3.3 ms steps) 10 ms to 6753 ms in 3.3 ms steps ms
V(UVP) Undervoltage detection range Nominal setting (50.6 mV steps) 1.012 V to 4.048 V in 50.6 mV steps V
V(UVP_ACC) Undervoltage detection voltage threshold accuracy(3) TA = +25°C, nominal setting between 1.012 V and 4.048 V(1) ±1.3 mV
TA = +25°C, nominal setting between 1.518 V and 3.542 V(1) –10 10 mV
TA = –10°C to +60°C, nominal setting between 1.012 V and 4.048 V(1) ±1.4 mV
TA = –10°C to +60°C, nominal setting between 1.518 V and 3.542 V(1) –15 15 mV
TA = –40°C to +85°C, nominal setting between 1.012 V and 4.048 V(1) ±1.6 mV
TA = –40°C to +85°C, nominal setting between 1.518 V and 3.542 V(1) –25 25 mV
V(UVP_DLY) Undervoltage detection delay(2) Nominal setting (3.3 ms steps) 10 ms to 6753 ms in 3.3 ms steps ms
V(SCD) Short circuit in discharge voltage threshold range Nominal settings, threshold based on VSRP - VSRN –10,
–20,
–40,
–60,
–80,
–100,
–125,
–150,
–175,
–200,
–250,
–300,
–350,
–400,
–450,
–500		 mV
V(SCD_ACC) Short circuit in discharge voltage threshold detection accuracy(3) TA = –40°C to +85°C, V(SCD) settings ≤ –20 mV –15 15 % of nominal threshold
TA = –40°C to +85°C, V(SCD) settings > –20 mV –35 35 % of nominal threshold
V(SCD_DLY) Short circuit in discharge detection delay Fastest setting (with 3 mV on VSRN – VSRP) 8 µs
Fastest setting (with 25 mV on VSRN – VSRP) 600 ns
Nominal setting (15 µs steps) 15 µs to 450 µs in 15 µs steps µs
V(OCC) Overcurrent in charge (OCC) voltage threshold range Nominal settings, threshold based on VSRP – VSRN 4 mV to 124 mV in 2 mV steps mV
V(OCD) Overcurrent in discharge (OCD1, OCD2) voltage threshold ranges Nominal settings, thresholds based on VSRP – VSRN –4 mV to –200 mV in 2 mV steps mV
V(OC_ACC) Overcurrent (OCC, OCD1, OCD2) detection voltage threshold accuracy(3) |Setting| < 20 mV –2 2.65 mV
|Setting| = 20 mV ~ 56 mV –4 4 mV
|Setting| = 56 mV ~ 100 mV –5 5 mV
|Setting| > 100 mV –7 5 mV
V(OC_DLY) Overcurrent (OCC, OCD1, OCD2) detection delay (independent delay setting for each protection) Nominal setting (3.3 ms steps) 10 ms to 425 ms in 3.3 ms steps ms
(1) Measured by fault triggered using 100 ms detection delay.
(2) Cell balancing not active. Timing of overvoltage and undervoltage protection checks is modified when cell balancing is in progress.
(3) Specified by a combination of characterization and production test