SLUSE13B
January 2020 – November 2021
BQ76952
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information BQ76952
7.5
Supply Current
7.6
Digital I/O
7.7
LD Pin
7.8
Precharge (PCHG) and Predischarge (PDSG) FET Drive
7.9
FUSE Pin Functionality
7.10
REG18 LDO
7.11
REG0 Pre-regulator
7.12
REG1 LDO
7.13
REG2 LDO
7.14
Voltage References
7.15
Coulomb Counter
7.16
Coulomb Counter Digital Filter (CC1)
7.17
Current Measurement Digital Filter (CC2)
7.18
Current Wake Detector
7.19
Analog-to-Digital Converter
7.20
Cell Balancing
7.21
Cell Open Wire Detector
7.22
Internal Temperature Sensor
7.23
Thermistor Measurement
7.24
Internal Oscillators
7.25
High-side NFET Drivers
7.26
Comparator-Based Protection Subsystem
7.27
Timing Requirements - I2C Interface, 100kHz Mode
7.28
Timing Requirements - I2C Interface, 400kHz Mode
7.29
Timing Requirements - HDQ Interface
7.30
Timing Requirements - SPI Interface
7.31
Interface Timing Diagrams
7.32
Typical Characteristics
8
Device Description
8.1
Overview
8.2
Functional Block Diagram
8.3
BQ76952 Device Versions
8.4
Diagnostics
9
Device Configuration
9.1
Commands and Subcommands
9.2
Configuration Using OTP or Registers
9.3
Device Security
9.4
Scratchpad Memory
10
Measurement Subsystem
10.1
Voltage Measurement
10.1.1
Voltage Measurement Schedule
10.1.2
Usage of VC Pins for Cells Versus Interconnect
10.1.3
Cell 1 Voltage Validation During SLEEP Mode
10.2
General Purpose ADCIN Functionality
10.3
Coulomb Counter and Digital Filters
10.4
Synchronized Voltage and Current Measurement
10.5
Internal Temperature Measurement
10.6
Thermistor Temperature Measurement
10.7
Factory Trim of Voltage ADC
10.8
Voltage Calibration (ADC Measurements)
10.9
Voltage Calibration (COV and CUV Protections)
10.10
Current Calibration
10.11
Temperature Calibration
11
Primary and Secondary Protection Subsystems
11.1
Protections Overview
11.2
Primary Protections
11.3
Secondary Protections
11.4
High-Side NFET Drivers
11.5
Protection FETs Configuration and Control
11.5.1
FET Configuration
11.5.2
PRECHARGE and PREDISCHARGE Modes
11.6
Load Detect Functionality
12
Device Hardware Features
12.1
Voltage References
12.2
ADC Multiplexer
12.3
LDOs
12.3.1
Preregulator Control
12.3.2
REG1 and REG2 LDO Controls
12.4
Standalone Versus Host Interface
12.5
Multifunction Pin Controls
12.6
RST_SHUT Pin Operation
12.7
CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
12.8
ALERT Pin Operation
12.9
DDSG and DCHG Pin Operation
12.10
Fuse Drive
12.11
Cell Open Wire
12.12
Low Frequency Oscillator
12.13
High Frequency Oscillator
13
Device Functional Modes
13.1
Overview
13.2
NORMAL Mode
13.3
SLEEP Mode
13.4
DEEPSLEEP Mode
13.5
SHUTDOWN Mode
13.6
CONFIG_UPDATE Mode
14
Serial Communications Interface
14.1
Serial Communications Overview
14.2
I2C Communications
14.3
SPI Communications
14.3.1
SPI Protocol
14.4
HDQ Communications
15
Cell Balancing
15.1
Cell Balancing Overview
16
Application and Implementation
16.1
Application Information
16.2
Typical Applications
16.2.1
Design Requirements (Example)
16.2.2
Detailed Design Procedure
16.2.3
Application Performance Plot
16.2.4
Calibration Process
16.3
Random Cell Connection Support
16.4
Startup Timing
16.5
FET Driver Turn-Off
16.6
Unused Pins
17
Power Supply Requirements
18
Layout
18.1
Layout Guidelines
18.2
Layout Example
19
Device and Documentation Support
19.1
Documentation Support
19.2
Support Resources
19.3
Trademarks
19.4
Electrostatic Discharge Caution
19.5
Glossary
20
Mechanical, Packaging, Orderable Information
Package Options
Mechanical Data (Package|Pins)
PFB|48
MTQF019B
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sluse13b_oa
sluse13b_pm
8.2
Functional Block Diagram