The I²C serial communications interface in the BQ76952 device acts as a responder device and supports rates up to 400 kHz with an optional CRC check. If the OTP is not programmed, the BQ76952 device will initially power up by default in 400 kHz I²C mode, although other versions of the device may initially power up in a different mode (as described in the Device Comparison Table. The OTP setting can be programmed on the manufacturing line, then when the device powers up, it automatically enters the selected mode per OTP setting. The host can also change the I²C speed setting while in CONFIG_UPDATE mode, then the new speed setting takes effect upon exit of CONFIG_UPDATE mode. Alternatively, the host can use the SWAP_TO_I2C() subcommand to change the communications interface to I²C immediately.

The I²C device address (as an 8-bit value including responder address and R/W bit) is set by default as 0x10 (write), 0x11 (read), which can be changed by configuration setting.

The communications interface includes programmable timeout capability. This should only be used if the bus will be operating at 100 kHz or 400 kHz. If this is enabled with the device set to 100-kHz mode, then the device will reset the communications interface logic if a clock is detected low longer than a t_TIMEOUT of 25 ms to 35 ms, or if the cumulative clock low responder extend time exceeds ≈25 ms, or if the cumulative clock low controller extend time exceeds 10 ms. If the timeouts are enabled with the device set to 400-kHz mode, then the device will reset the communications interface logic if a clock is detected low longer than t_TIMEOUT of 5 ms to 20 ms. The bus also includes a long-term timeout if the SCL pin is detected low for more than 2 seconds, which applies whether or not the timeouts above are enabled.

Figure 14-1 shows an I²C write transaction. Block writes are allowed by sending additional data bytes before the Stop. The I²C logic will auto-increment the register address after each data byte.

When enabled, the CRC is calculated as follows:

• In a single-byte write transaction, the CRC is calculated over the responder address, register address, and data.
• In a block write transaction, the CRC for the first data byte is calculated over the responder address, register address, and data. The CRC for subsequent data bytes is calculated over the data byte only.

The CRC polynomial is x⁸ + x² + x + 1, and the initial value is 0.

When the responder detects an invalid CRC, the I²C responder NACKs the CRC, which causes the I²C responder to go to an idle state.

Figure 14-1 I²C Write

Figure 14-2 shows a read transaction using a Repeated Start.

Figure 14-2 I²C Read with Repeated Start

Figure 14-3 shows a read transaction where a Repeated Start is not used; for example, if not available in hardware. For a block read, the controller ACKs each data byte except the last and continues to clock the interface. The I²C block auto-increments the register address after each data byte.

When enabled, the CRC for a read transaction is calculated as follows:

• In a single-byte read transaction, the CRC is calculated beginning at the first start, so includes the responder address, the register address, then the responder address with a read bit set, then the data byte.
• In a block read transaction, the CRC for the first data byte is calculated beginning at the first start and will include the responder address, the register address, then the responder address with a read bit set, then the data byte. The CRC resets after each data byte and after each stop. The CRC for subsequent data bytes is calculated over the data byte only.

The CRC polynomial is x⁸ + x² + x + 1, and the initial value is 0.

When the controller detects an invalid CRC, the I²C controller will NACK the CRC, which causes the I²C responder to go to an idle state.

Figure 14-3 I²C Read Without Repeated Start