SLUSE13B January 2020 – November 2021 BQ76952
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VBAT | Supply voltage | Voltage on BAT pin (normal operation) | 4.7 | 80 | V | |
VBAT | Supply voltage(4) | Voltage on BAT pin (OTP programming) | 10 | 12 | V | |
TOTP | OTP programming temperature(4) | -40 | 45 | °C | ||
VPORA | Power-on reset | Rising threshold on BAT | 3 | 4 | V | |
VPORA_HYS | Power-on reset hysteresis | Device shuts down when BAT < VPORA - VPORA_HYS | 180 | mV | ||
VWAKEONLD | Wake on LD voltage | Rising edge on LD, with BAT already in valid range | 0.8 | 1.45 | 2.25 | V |
VWAKEONTS2 | Wake on TS2 voltage | Falling edge on TS2, with BAT already in valid range. TS2 will be weakly driven with a ≈ 5 V level during shutdown. | 0.7 | 1.1 | V | |
VIN | Input voltage range(4) | PACK, LD | 0 | 80 | V | |
VIN | Input voltage range(4) | PCHG, PDSG | the maximum of VBAT-9 or VLD-19 | 80 | V | |
VIN | Input voltage range(4) | REG1, REG2, RST_SHUT, ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF, DCHG, DDSG, except when the pin is being used for general purpose ADC input or thermistor measurement. | 0 | 5.5 | V | |
VIN | Input voltage range(4) | TS1, TS2, TS3, CFETOFF, DFETOFF, DCHG, DDSG, ALERT, HDQ, when the pin is configured for general purpose ADC input or thermistor measurement. | 0 | VREG18 | V | |
VIN | Input voltage range(4) | SRP, SRN, SRP-SRN (while measuring current) | –0.2 | 0.2 | V | |
VIN | Input voltage range(4) | SRP, SRN (without measuring current) | –0.2 | 0.75 | V | |
VIN | Input voltage range(4) (5) | VVC(0) | –0.2 | 0.5 | V | |
VIN | Input voltage range(4) | VVC(x), 1 ≤ x ≤ 4 | maximum of VVC(x–1) – 0.2 or VSS–0.2 | minimum of VVC(x–1)+5.5 or VSS+80 | V | |
VIN | Input voltage range(4) | VVC(x), x ≥ 5 | maximum of VVC(x–1) – 0.2 or VSS + 2.0 | minimum of VVC(x–1) + 5.5 or VSS + 80 | V | |
RC | External cell input resistance(4) (7) | 20 | 100 | Ω | ||
CC | External cell input capacitance(4) (7) | 0.1 | 0.22 | 1 | µF | |
VO | Output voltage range | LD | 80 | V | ||
VO | Output voltage range(6) | CHG, DSG, CP1 | 85 | V | ||
TOPR | Operating temperature(6) | –40 | 85 | °C | ||
VCELL(ACC) | Cell voltage measurement accuracy | 2 V < VVC(x) - VVC(x-1) < 5 V, TA = 25°C, 1 ≤ x ≤ 16(2) (3) | –5 | 5 | mV | |
VCELL(ACC) | Cell voltage measurement accuracy(6) | 2 V < VVC(x) - VVC(x-1) < 5 V, TA = 0°C to 60°C, 1 ≤ x ≤ 16(2) (3) | –10 | 10 | mV | |
VCELL(ACC) | Cell voltage measurement accuracy(6) | –0.2 V < VVC(x) - VVC(x-1) < 5.5 V, TA = -40°C to 85°C, 1 ≤ x ≤ 16(2) (3) | –15 | 15 | mV | |
VSTACK(ACC) | Stack voltage (VC16 - VSS) measurement accuracy(6) | 0 V < VVC16 - VVSS < 80 V, TA = -40°C to 85°C(2) | –0.5 | 0.5 | V | |
VPACK(ACC) | PACK pin voltage measurement accuracy(6) | 0 V < VPACK < 80 V, TA = -40°C to 85°C(2) | –0.5 | 0.5 | V | |
VLD(ACC) | LD pin voltage measurement accuracy(6) | 0 V < VLD < 80 V, TA = -40°C to 85°C(2) | –0.5 | 0.5 | V |